彩灯实验报告

1、设计八 彩灯控制器要求：1、 设计一个彩灯控制器，使彩灯（led管）能连续发出四种以上不同的显示形式；2、随着彩灯显示形式的变化，发出不同的音响声。设计提示:1、彩灯显示的不同形式可由不同进制计数器驱动led显示完成；2、 音响由选择不同频率cp脉冲驱动扬声器形成；3、 彩灯显示形式由实验箱中拨码开关控制。实验程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity caidengkongzhiqi isport(clk1,rst,clk2 : instd_logic;caideng :

2、out std_logic_vector(7 downto 0);cz:in std_logic_vector(1 downto 0);speaker: out std_logic);end caidengkongzhiqi;architecture one of caidengkongzhiqi iscomponent counter_8port(clk,rst : instd_logic;count_out : out integer range 0 to 7);end component ;component caidengkongzhiport(ins:in std_logic_vec

3、tor(1 downto 0);input : in integer range 0 to 7;rst:in std_logic; output : out std_logic_vector(7 downto 0);end component ;component fenpinqiport(clk,rst: instd_logic;clk_10,clk_4,clk_6,clk_8 : out std_logic);end component ;component xzq4_1port( rst:in std_logic; inp:in std_logic_vector(1 downto 0);

4、in1,in2,in3,in4: in std_logic;output : out std_logic);end component ;signal s,g,m,n,k :std_logic; signal f:integer range 0 to 31;signal w:integer range 0 to 3;beginu1: counter_8 port map (clk=clk1, rst=rst, count_out =f);u2: caidengkongzhi port map (ins=cz,input=f, rst=rst, output =caideng);u3: fenp

5、inqi port map (clk=clk2, rst=rst, clk_10=g, clk_4=m, clk_6=n, clk_8=k);u4: xzq4_1 port map (inp=cz,rst=rst, in1=g, in2=m, in3=n, in4=k, output=speaker);end one;library ieee;use ieee.std_logic_1164.all;entity fenpinqi isport(clk,rst: instd_logic;clk_10,clk_4,clk_6,clk_8: out std_logic);end fenpinqi;a

6、rchitecture cd of fenpinqi isbeginp1:process(clk,rst) variable a:integer range 0 to 20; begin if rst=1 then clk_4=3 then a:=0; clk_4=1; else a:=a+1; clk_4=0; end if; end if; end if;end process p1;p2:process(clk,rst) variable b:integer range 0 to 20; begin if rst=1 then clk_6=5 then b:=0; clk_6=1; el

7、se b:=b+1; clk_6=0; end if; end if; end if;end process p2;p3:process(clk,rst) variable c:integer range 0 to 20; begin if rst=1 then clk_8=7 then c:=0; clk_8=1; else c:=c+1; clk_8=0; end if; end if; end if;end process p3;p4:process(clk,rst) variable d:integer range 0 to 20; begin if rst=1 then clk_10

8、=9 then d:=0; clk_10=1; else d:=d+1; clk_10=0; end if; end if; end if;end process p4;end cd;library ieee;use ieee.std_logic_1164.all;entity xzq4_1 isport( rst:in std_logic; inp:in std_logic_vector(1 downto 0);in1,in2,in3,in4: in std_logic;output: out std_logic);end xzq4_1;architecture a of xzq4_1 is

9、beginprocess (rst,inp)begin if(rst=1) then outputoutputoutputoutputoutputnull; end case; end if;end process;end a;library ieee;use ieee.std_logic_1164.all;entity counter_8 isport(clk,rst: instd_logic;count_out: out integer range 0 to 7);end counter_8;architecture a of counter_8 isbeginprocess (rst,c

10、lk) variable temp:integer range 0 to 8;beginif rst=1 then temp:=0;elsif (clkevent and clk=1) then temp:=temp+1; if(temp=8) then temp:=0; end if;end if; count_out=temp;end process;end a;library ieee;use ieee.std_logic_1164.all;entity caidengkongzhi isport(ins:in std_logic_vector(1 downto 0);input: in

11、integer range 0 to 7; rst:in std_logic; output: out std_logic_vector(7 downto 0); end caidengkongzhi;architecture a of caidengkongzhi isbeginprocess (input)begin if rst=1 then outputoutputoutputoutputoutputoutputoutputoutputoutputnull;end case;elsif(ins=01) thencase input iswhen 0=outputoutputoutputoutputoutputoutputoutputoutputnull; end case;elsif(ins=10)thencase input is when 0=outputoutputoutputoutputoutputoutp