进制同步计数器设计报告.docx

1、浙江万里学院实验报告成绩：课程名称：可编程逻辑器件应用教师：施炯实验名称： 100 进制同步计数器设计专业班级：电子103 姓名：徐强学号： 2018014092 实验日期： 2018.5.10一、实验目的：1、掌握计数器的原理及设计方法；2、设计一个 0100的计数器；3、利用实验二的七段数码管电路进行显示；二、实验要求：1、用 VHDL 语言进行描写；2、有计数显示输出；3、有清零端和计数使能端；三、实验结果：1. VHDL 程序LIBRARY IEEE 。USE IEEE.STD_LOGIC_1164.ALL 。PACKAGE my_pkg ISComponent nd2-或门PORT

2、(a,b: IN STD_LOGIC。c: OUT STD_LOGIC 。END Component。Component led_decoderPORT (din:in std_logic_vector(3 downto 0 。 -四位二进制码输入 seg:out std_logic_vector(6 downto 0 。 -输出 LED 七段码END Component。Component CNT60 -2 位 BCD 码 60 进制计数器PORT(CR:IN STD_LOGIC 。EN:IN STD_LOGIC 。CLK:IN STD_LOGIC 。OUTLOW:BUFFER STD_LO

3、GIC_VECTOR(3 DOWNTO 0 。OUTHIGH:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0。END Component。Component CNT100 -带使能和清零信号的100 进制计数器PORT(CLK:IN STD_LOGIC 。EN:IN STD_LOGIC 。CLR:IN STD_LOGIC 。OUTLOW:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0 。OUTHIGH:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0。END Component。Component freq_div-50MHZ 时

4、钟分频出 1HzPORT(clkinput : IN STD_LOGIC 。output : OUT STD_LOGIC。END Component。2 / 8Component jtd-交通灯控制器PORT(CLKIN:IN STD_LOGIC 。-50MHZR1,G1,R2,G2,R3,G3,R4,G4:OUT STD_LOGIC。 -红绿灯信号输出 GAO,DI:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0 - 倒计时输出。END Component。END my_pkg。LIBRARY IEEE 。USE IEEE.STD_LOGIC_1164.ALL 。USE

5、 work.my_pkg.ALL 。-打开程序包ENTITY Demo3 ISPORT (CRl:IN STD_LOGIC 。ENl:IN STD_LOGIC 。CLKIN: IN STD_LOGIC 。LEDLOW,LEDHIGH: OUT STD_LOGIC_VECTOR(6 downto 0。END Demo3。ARCHITECTURE behv OF Demo3 ISSIGNAL CLKTEMP: STD_LOGIC 。-定义中转信号SIGNAL LEDLOWTEMP,LEDHIGHTEMP:STD_LOGIC_VECTOR(3 downto 0。BEGINu1:freq_div PO

6、RT MAP(CLKIN,CLKTEMP 。-位置关联方式u2:CNT60 PORTMAP(CR=CRl,EN=ENl,CLK=CLKTEMP,OUTLOW=LEDLOWTEMP,OUTHIGH=LEDHIGHTEMP。-名字关联方式3 / 8u3:led_decoder PORT MAP(LEDLOWTEMP,LEDLOW 。-低位数码管输出u4:led_decoder PORT MAP(LEDHIGHTEMP,LEDHIGH 。-高位数码管输出END behv。LIBRARY ieee 。USE ieee.std_logic_1164.all。ENTITY freq_div ISPORT(

7、clkinput : IN STD_LOGIC 。output : OUT STD_LOGIC。END freq_div 。ARCHITECTURE rt OF freq_div ISSIGNAL count_signal : INTEGERRANGE 0 TO 25000000 。signal mid1 : STD_LOGIC 。BEGINPROCESS (clkinputBEGINIF (clkinputEVENT AND clkinput = 1 THENif count_signal=24999999 then -50MHz division to 1Hz count_signal =

8、 0。mid1= not mid1。elsecount_signal = count_signal + 1。4 / 8end if。output 。 -四位二进制码输入 seg:out std_logic_vector(6 downto 0 。 -输出 LED 七段码end led_decoder。architecture Behavioral of led_decoder isbeginprocess(dinbegincase din iswhen 0000 =seg seg seg seg seg seg seg seg seg seg seg 。OUTHIGH:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0。END CNT60 。ARCHITECTURE behav OF CNT60 ISBEGINPROCESS(CLK,CR,ENBEGINif CR=1 thenOUTHIGH=0000 。OUTLOW=0000 。elsif EN =1thenIF CLKEVENT AND CLK=1 THEN6 / 8IF OUTHIGH=1001 AND OUTLOW=1001 THENOUTHIGH=0000 。OUTLOW=0000 。ELSIF OUTLOW=1001 THENOU