常见面试笔试题-verilog程序库

1、加减法module addsub( input 7:0 dataa,input 7:0 datab,input add_sub,/ if this is 1, add; else subtractinput clk,output reg 8:0 result );always (posedge clk)begin/or assign cout,sum=dataa+datab;if (add_sub) result = dataa + datab;else result 1101，然后和8，亦即1000相加就会得到5，亦即0101。至于溢岀的最高位可以无视掉。乘法器module mult(out

2、come,a,b);parameter SIZE=8;inputSIZE:1 a,b;output reg2*SIZE:1 outcome;integer i;always (a or b)begin outcome=0;for(i=0,i=SIZE;i=i+1)if(bi) outcome=outcome+(a(i-1);endendmodule另一种乘法器。在初始化之际，取乘数和被乘数的正负关系，然后取被乘数和乘数的正值。输出结果根据 正负关系取得。else if( Start_Sig )case(i)0:beginisNeg = Multiplicand人 Multiplier7;Mca

3、nd = Multiplicand ?(Multiplicand + 1b1 ) : Multiplicand; Mer = Multiplier ?(Multiplier + 1b1 ) : Multiplier;Temp = 16dO;i = i + 1b1;end1:/ Multiplingif( Mer = 0 ) i = i + 1b1;else begin Temp = T emp + Mcand; Mer = Mer - 1b1; end2:begin isDone = 1b1; i = i + 1b1; end3:begin isDone = 1b0; i = 2d0; end

4、endcaseassign Done_Sig = isDone;assign Product = isNeg ?(Temp + 1b1 ) : Temp;endmodulebooth 乘法器module booth_multiplier_module(input CLK,input RSTn,input Start_Sig,input 7:0A,input 7:0B,output Done_Sig,output 15:0Product,output 7:0SQ_a,output 7:0SQ_s,output 16:0SQ_p);reg 3:0i;reg 7:0a;/ result of Are

5、g 7:0s;/ reverse result of Areg 16:0p;/ p 空间，16+1 位reg 3:0X;/指示n次循环reg isDone;always ( posedge CLK or negedge RSTn )if( !RSTn )begini = 4d0;a = 8d0;s = 8d0;p = 17d0;X = 4d0;isDone = 1bO;endelse if( Start_Sig )case(i)0:begin a = A; s =(A + 1b1 ); p = 8dO , B , 1bO ; i = i + 1b1; end1:if( X = 8 ) begi

6、n X = 4dO; i = i + 4d2; endelse if( p1:0 = 2b01 ) begin p = p16:9 + a , p8:0 ; i = i + 1b1; endelse if( p1:0 = 2b10 ) begin p = p16:9 + s , p8:0 ; i = i + 1b1; endelse i = i + 1b1;00 和 11，无操作2:0 or 1.begin p = p16 , p16:1 ; X = X + 1b1; i = i - 1b1; end/ 右移，最高位补3:begin isDone = 1b1; i = i + 1b1; end

7、4:begin isDone = 1b0; i = 4d0; endendcaseassign Done_Sig = isDone;assign Product = p16:1;endmodule除法器module divider_module(input CLK,input RSTn,input Start_Sig,input 7:0Dividend,input 7:0Divisor,output Done_Sig,output 7:0Quotient,output 7:0Reminder,);reg 3:0i;reg 7:0Dend;reg 7:0Dsor;reg 7:0Q;reg 7:0

8、R;reg isNeg;reg isDone;always ( posedge CLK or negedge RSTn )if( !RSTn )begini = 4dO;Dend = 8dO;Dsor = 8dO;Q = 8dO;isNeg = 1bO;isDone = 1bO;endelse if( Start_Sig )case(i)O:beginDend = Dividend7 ? Dividend + 1b1 : Dividend;Dsor = Divisor7 ? Divisor :(Divisor + 1b1 );isNeg = Dividend7 A Divisor7;i Den

9、d )begin Q = isNeg ?(Q + 1b1 ) : Q; i = i + 1b1; endelse begin Dend = Dend + Dsor; Q = Q + 1b1; end2: begin isDone = 1b1; i = i + 1b1; end3: begin isDone = 1bO; i b) begin n=a-b;m=4bOOO1; state=S1; endelse begin m=4bOOOO;n=a; state=b) begin m=m+1;n=n-b;state=S1;endelse begin state=S2;endendS2: begin

10、 result=m;yu=n;state=SO;enddefule:state=SO;endcaseend endmodule13、一个可预置初值的7进制循环计数器 verilogmodule count(clk,reset,load,date,out);input load,clk,reset;input3:0 date;output reg3:0 out;parameter WIDTH=4d7;always(clk or reset)beginif(reset) out=4d0;else if(load) out=date;else if(out=WIDTH-1) out=4d0;else

11、out=out+1;endendmoduleJohnson 计数器约翰逊(Johnson)计数器又称扭环计数器，是一种用n位触发器来表示2n个状态的计数器。它与环形计数 器不同，后者用n位触发器仅可表示n个状态。n位二进制计数器(n为触发器的个数)有2切 个状态。若以 四位二进制计数器为例，它可表示16个状态。“0000-1000-1100-1110-1111-0111-0011-0001-0000-1000”module Johnson(input clk,input clr,output regN-1:0 q);always(posedge clk or negedge clr)if(!c

12、lr)qv=N1 b0else if(!q0)q=1 b1,qN-1:1;elseq=1 b0,qN-1:1;endmodule任意分频，占空比不为50%always(clk)begin if(count=x-1) count=0;else count=count+1; endassign clkout=county/y 一般用 count 的最高位偶数分频(8分频，占空比50%)(计数至n-1 ,翻转)module count5(reset,clk,out)input clk,reset;output out;reg1:0 count;always(clk)if(reset) begin c

13、ount=0; out=0; endelse if(count=3) begin count=0;out=!out: endelse count=count+1;endmodule奇数分频电路(占空比 50% )。module count5(reset,clk,out)input clk,reset;output out;reg2:0 m,n;reg count1;reg count2; always(posedge clk)beginif(reset) beginmv=0;count1=0;endelse begin if(m=4) m=0; else m=m+1;/ “ 4”为分频数NUM

14、-1,NUM=5if(m2) count1=1; else count1=0;endend always(negedge clk)beginif(reset) begin n=0;count2=0;endelse begin if(n=4) n=0; else n=n+1;if(n2) count2=1; else count2=0;endend assign out=count1|count2;半整数分频締出时钟入时忖ilkm斤说门图9.1 K iV-0.5 t K数井频器is理国module fdiv5_5(clkin,clr,clkout)input clkin,clr; output

15、reg clkout;reg clkl; wire clk2; integer count;xor xor1(clk2,clkin,clk1)always(posedge clkout or negedge clr)begin if(clr) begin clk1=1 b0; endelse clk1=clk1;endalways( posedge clk2 or negedge clr)begin if(clr)begin count=0; clkout=1 b0; endelse if(count=5)begin count=0; clkout=1 b1; endelse begin co

16、unt=count+1; clkout=1 b0; endendendmodule小数分频N=M/P . N为分配比，M为分频器输入脉冲数，P为分频器输出脉冲数N=(8 X9+9 X1)/ (9+1 ) =8.1 先做9次8分频再做1次9分频。 module fdiv8_1(clkin,rst,clkout)input clkin,rst; output reg clkout;reg3:0 cnt1,cnt2;always(posedge clkin or posedge rst)begin if(rst) begin cnt1=0;cnt2=0;clkout=0; end08else if(

17、cnt19)/cnt1,beginif(cnt27) begin cnt2=cnt2+1;clkout=0; endelse begin cnt2=0;cnt1=cnt1+1;clkout=1; endendelse begin/cnt1,if(cnt28) begin cnt2=cnt2+1;clkout=0; endelsebegin cnt2=0;cnt1=0;clkout=1;endendendendmodule串并转换module p2s(clk,clr,load,pi,so)input clk,clr,load;input 3:0 pi;output so;reg3:0 r;alw

18、ays(posedge clk or negedge clr)if(clr) r=4h0;else if(load) r=pi;else r=r, 1b0;/ or r1;assign so=r3;endmodule module s2p(clk,clr,en,si,po)input clk,clr,en,si;output3:0 po;always(posedge clk or negedge clr)if(clr)r=8 ho;elser=r,si;assign po=(en) ? r : 4 h0;endmoduleb)试用VHDL或VERILOG、ABLE描述8位D触发器逻辑modul

19、e dff(q,qn,d,clk,set,reset)input7:0 d,set;input clk,reset;output reg7:0 q,qn;always (posedge clk)beginendif(reset) begin qv=8 hOO; qn=8 hFF; endelse if(set) begin q=8 hFF; qn=8 hOO;else begin q=d; qn=d; endendendmodule序列检测“101 ”module xulie101(clk,clr,x,z);input clk,clr,x;output reg z;reg1:0 state,n

20、ext_state;parameter s0=2b00,s1=2b01,s2=2b11,s3=2b10;always (posedge clk or posedge clr)begin if(clr) state=s0;else state=next_state;endalways (state or x)begincase(state)s0:begin if(x)next_state=s1;elsenext_state=s0;ends1:begin if(x)next_state=s1;elsenext_state=s2;ends2:begin if(x)next_state=s3;else

21、next_state=s0;ends3:begin if(x)next_state=s1;elsenext_state=s2;enddefault: next_state=s0;endcaseendalways (state)begin case(state)s3:z=1;default:z=0;endcaseendendmodule按键消抖1.采用一个频率较低的时钟，对输入进行采样，消除抖动。module switch(clk,keyi n,keyout)parameter COUNTWIDTH=8;in put clk,keyi n;output reg keyout; regCOUNTW

22、IDTH-1:O cou nter;wire clk_use;/频率较低的时钟assig nclk_use=cou nterCOUNTWIDTH-1;always(posegde clk)counter=counter+1 b1;always(posedge clk_use)keyout=key in;en dmodule2. module switch(clk,keyi n,keyout)parameter COUNTWIDTH=8;in put clk,keyi n;output reg keyout; regCOUNTWIDTH-1:O cou nter;in itialcoun ter

23、=0,keyout=0,key in=0;always(posegde clk)if(key in=1) beg in key_m=keyi n, coun ter=co un ter+1;e ndelse coun ter=0;if(keyin&counterm) keyout=1;m 定义时延en dmodule数码管显示module number_mod_module/分别取得数字的十位和个位(CLK, RSTn, Number_Data, Ten_Data, One_Data);input CLK;input RSTn;input 7:0Number_Data;output 3:0Te

24、n_Data;output 3:0One_Data;reg 31:0rTen;reg 31:0rOne;always ( posedge CLK or negedge RSTn )if( !RSTn )beginrTen = 32d0; rOne = 32d0;endelsebeginrTen = Number_Data / 10; rOne = Number_Data % 10; endassign Ten_Data = rTen3:0;assign One_Data = rOne3:0;endmodule/数码管显示module led(CLK, Ten_Data, One_Data,le

25、d0, ledl);input 3:0 Ten_Data, One_Data;input CLK;output 7:0 led0, ledl;reg 7:0 led0, ledl;always ( posedge cp_50)begincasez (One_Data)4d0 : led0 = 8b1100_0000;4d1 : led0 = 8b1111_1001;4d2 : led0 = 8b1010_0100;4d3 : led0 = 8b1011_0000;4d4 : led0 = 8b1001_1001;4d5 : led0 = 8b1001_0010;4d6 : led0 = 8b1

26、000_0010;4d7 : led0 = 8b1111_1000;4d8 : led0 = 8b1000_0000;4d9 : led0 = 8b1001_0000; default:led0 = 8b1111_1111;endcasecasez (Ten_Data)4d0 : ledl = 8b1100_0000;4d1 : ledl = 8b1111_1001;4d2 : ledl = 8b1010_0100;4d3 : ledl = 8b1011_0000;4d4 : ledl = 8b1001_1001;4d5 : ledl = 8b1001_0010;4d6 : ledl = 8b

27、1000_0010;4d7 : ledl = 8b1111_1000;4d8 : ledl = 8b1000_0000;4d9 : ledl = 8b1001_0000;default:led0 = 8b1111_1111;endcaseendendmodule5. fifo 控制器.FIFO存储器FIFO是英文First In First Out的缩写，是一种先进先出的数据缓存器，他与普通存储器的 区别是没有外部读写地址线，这样使用起来非常简单，但缺点就是只能顺序写入数据，顺序的读岀数据， 其数据地址由内部读写指针自动加1完成，不能像普通存储器那样可以由地址线决定读取或写入某个指定的地址。在

28、系统设计中，以增加数据传输率、处理大量数据流、匹配具有不同传输率的系统为目的而广泛使用FIFO存储器，从而提高了系统性能.FIFO参数：FIFO的宽度，the width ，指FIFO 一次读写操作的数据位；FIFO深度，THE DEEPTH，指FIFO可以存储多少个 N位的数据；满标志，FIFO已满或将要满时送出的一个信号，以阻止 FIFO的血操作继续向FIFO中写数据而造成溢出 (overflow )；空标志，阻止FIFIO的读操作；module fifo_module(input CLK,input RSTn,input Write_Req,input 7:0FIFO_Write_Dat

29、a,input Read_Req,output 7:0FIFO_Read_Data,output Full_Sig,output Empty_Sig,*/output 7:0SQ_rS1,output 7:0SQ_rS2,output 7:0SQ_rS3,output 7:0SQ_rS4,output 2:0SQ_Count/*/);iisisisisisisisiskkkkkkkkkkkkkkkkkkkkkkkkkkparameter DEEP = 3d4;reg 7:0rShift DEEP:0;reg 2:0Count;reg 7:0Data;always ( posedge CLK o

30、r negedge RSTn )if( !RSTn )beginrShift0 = 8d0; rShift1 = 8d0; rShift2 = 8d0;rShift3 = 8d0; rShift4 = 8d0;Count = 3d0;Data = 8d0;endelse if( Read_Req & Write_Req & Count 0 ) beginrShift1 = FIFO_Write_Data;rShift2 = rShift1;rShift3 = rShift2;rShift4 = rShift3;Data = rShift Count ;endelse if( Write_Req

31、 & Count DEEP ) beginrShift1 = FIFO_Write_Data;rShift2 = rShift1;rShift3 = rShift2;rShift4 = rShift3; Count 0 ) beginData = rShiftCount;Count = Count - 1b1;endassign FIFO_Read_Data = Data;assign Full_Sig = ( Count = DEEP ) ? 1b1 : 1b0;assign Empty_Sig = ( Count = 0 ) ? 1b1 : 1b0;assign SQ_rS1 = rShi

32、ft1; assign SQ_rS2 = rShift2;assign SQ_rS3 = rShift3; assign SQ_rS4 = rShift4;assign SQ_Count = Count;I*Endmodulefifi 2(指针控制)module FIFO(date,q,clr,clk,we,re,ff,ef); parameter WIDTH=8,DEEPTH=8,ADDR=3; input clk,clr;input we,re;inputWIDTH-1:0 date;output ff,ef;output regWIDTH-1:0 q;/写地址regWIDTH-1:0 m

33、em_dateDEEPTH-1:0; regADDR-1:0 waddr,raddr; reg ff,ef;always(posedge clk or negedge clr)begin if(!clr) waddr=0;else if(we=1 &ff=0) waddr=waddr+1;else if(we=1 & ff=0&waddr=7) waddr=0;endalways(posedge clk)begin if(we& !ff) mem_datewaddr=date;endalways(posedge clk or negedge clr)/ 读地址begin if(!clr) ra

34、ddr=0;else if(re=1 &ef=0) raddr=waddr+1;else if(re=1 &ef=0&raddr=7) raddr=0;endalways(posedge clk)begin if(re&!ef) q=mem_dateraddr; endalways(posedge clk or negedge clr)begin if(!clr) ff=1b0;else if(we & !re) & (waddr=raddr-1) | (waddr=DEEPTH-1) & (raddr=1b0)ff=1b1;else ff=1b0;endalways(posedge clk or negedge clr)begin if(!clr) ef=1b0;else if(!we