ADS1278使用总结

1、1.数据输出格式INPUT SIGNAL V,nIDEAL OUTPUTCQDE(AINP-AINN)王 +VheF7FFFFFh+ *EF2鸽-1000001h0OOOOOOh一 VrefFFFFFFh2卸-1-5ef(223 1 )eoooooh(1) Excludes effects of noise, INL, offset, and gain errors.2.引脚说明NAUEPIMNO,FUNC71QHDESCniPIlQHAGhOe. 43., 54se. 5HAtiihig grouTKlAnatoqiound： conibKl b DGND Lding b siinglH p

2、iwa.AINPlaAnalog lnpi4WNP?1AnabQ inputAiNPa63Analog InputADS1Z7S:AIH.PB-1 Positive analog InpK channels fl dviough 1flINPleiAnalog InputAINPS轩AnskJfl inputADS13T4：A/llN.P|a51 Corvwd袒 to rrlafnaJ ESD Fils The rputs may floatAINP&49Analog inputAIKP|4:1J Pgsrt- analog input channs A lirough 1.A(NP747Ar

3、idkx) InputAINPS45Analog inpi/tJPINFUNCTION Analog inputDESCRIPTQNNAMEAINN1NO.4J AlhN22Analog inpu*1 AJNN364Analog irpulADS127t: AINNpJ lefiath/d analog hput channel 8 through 1.AINM462Analog inputAIISNS92Analog IrpulADS1274： AlhN|S:S Cornecttd D menial ESQ rails. The hiputt nay float1 AlhN6soAnalog

4、 inputAINNf4 Janalog npui.chaniefc 4 llroug*i 1.AlhM748Anolg inputAlhNfi46Analog irpmAVDO5 44.53,60Aralcg powe supply&nlog power 5Uppt/ (4 75V to 5 25V),VCOM55Analog oupvlAVDO2 Unbuitoted volume output.VREFN57Analog inputNeatve reference cputVREFP56AmIoo fnpuiPofttive referenc* bipii.1 CLK27Digiw in

5、puiMaslu clocK Input (tix)CLKDIV10Digiiai inpuiCLK irpii dvidfw control1 37MH? (high-SpeRd modepMherwiM 27MH70 13.5MH2 (kw-pcwef)/&4MH: (towhsprad)DAND7,21.24.35Oigtal groundOlQUri ORMjnd po)ver ttfpplyDIN12Oiylia! IrpulDahyOiam outa irtpuv1 DOUT120Otgfe 創 oupulBOUTl U IDM dau output iTDM nnde).19Di

6、gitalDOUT318DgCal outpttADS127: DOU181 Data ouiput for channels 8 Throuah 1.DOUT417Digital ouipuDOUT516DqI oupttADS 1274； DOUTie 旬 IntomoNy oonoctod to Ktrvo circuitry; outputs amDOUT815DiQtAi ompttdrivenDOUTI4 1 Data output for chon rale 4 thpuh 1.I DOUT714OF 創 MM1 DOUT313DkXal ouEpttDRDV/ FSYNC29D

7、igtalinfXJtKJtp(itFra*ne-Sync protocol: kane dock input SPI protocol： data ready outputovoo26Dgital power stpplyDigtal cere power supplyFORMATO32Digital inouiFORMA7120I Seeds Pranie-Sync/SPI protccol TDMciscrete data outputs. (oced/Oynamc po$ion TDM daia and nodutalor nodaxmial operaing mode.rORMATl

8、31DiiW inpulFORMAT230Digilai inpuilOVDO?2, 23OgHal powr lupply10 pow(r supply (*1 6SV lo 3.6V)NODEO34Mgiw irtMJiMODE1:0 Selects High-Spoed. High-Resolution. Lew-Power, a Low-Soeed1 MODE133Digital inputnxxle optrabon.42DiglW InputPWDN241ENgnaurpui40Digital inpifiADS1278:PW0N|81| Power-down control fa

9、r chanrels 8 through 1,FW0N439DigiiAi inpulPWDN538Digital irxnrADS1274; PWDM&Sj must OVPW0N637呦“ incM/1PWO14:1| Powerxtown control tor chanrels 4 through 1.PW0N730Oigig irpulI PWDN835Digital InputSCLK28CUgtalinputMiSoral clock input. ModulMor clock output.SYNC11Digiiai inpuiSynchrorize irpu (all cha

10、nnels).lESTO8MoitalinDutTESTll :0| lest moo select no , Mermai ofxmiM01 * Do not jseTESTI9Digital inputll=Tt mode10-Do not JSe3. 速度模式设置芯片一共有4种速度模式，下图为 4种模式的最大采样率及功耗表:UOHMrgtvSpted UAK DATA RAT 专PSI144 saiPASSBAND 4 切SMRin6MOISC 山哥y*BAPOWERHAIWEL (EW2H 盼 mneslutEan1S2Z23.別 gno5.564Loh-Powm2S.SBBtasB与

11、ai1呻了50107BO7以上四种工作模式用 MODE和MODE控制，其对应关系如下表，当为High-Speed时，fclk最大可为37MHz其他三种模式时，最大输入时钟为27MHz且当fclk27MHz时,只能采用Frame-Sync方式读取数据。MODE1 DJMODE SELECTIONMWtf爾JUDOHigh-Speed144,53101High-fi esol Lrtion52,73410Low Power52,73411Low Sp&ed10,547(1) (cLK - 27MHz max (37MH2 max in High Speed mode).在High-Speed模式下

12、，不同的时钟频率(fclk) 对DVDD和参考电压(Vref)的的要求也 不一样，具体如下表所示：kLK (MHi)Vref (V)DVDD(V)INTERFACE0.1 fg270.5 to3J1.&5to 1IJ95IFrame Syoc w SPI27 fqm S 32768 5 to2.1.65 to ll：95Frame-Sync32.760 tcLh E 372.12.i0 to 22Frame-SyncADS1278的数据输出率与fcik具有固定的比例关系，且Low-Power和Low-Speed模式下，CLKDIV能够对fclk分频。另外两种模式下，CLKDIV必须为1,具体关

13、系如下表所示：MOPESELECTIONMAX feui (iMHz)CLKDIVfciK foATADATA HATt (SPS)High-Speed371256144 531HighResobliop271&1252734Lo-Pwer271S1252.73413.502SGLow，Speed2712.56010,5475 4Q512注意：在High-Speed模式下，若为TDM方式输出，因为8个通道均通过 OUT1输出且数据为24bits，故必须保证clk=SCLK4. 输出方式设置采样数据可通过两种方式输出SPI方式和Frame-Sync方式。输出方式由 FORMAT2:0控制，如下图

14、所示。TDM表示8个通道数据全部由 DUOT1输出，CH1在前，CH8在后。此时 若DATA POSITION为Dynamic则表示：若某通道关闭，则该通道仍然输出，输出数据为 若DATAPOSITION为Fixed ,则如果某通道关闭，则该通道不输出，直接输出下一通道数据。Table 14. Data Output FormatFOflMAT2:0OOOIMTEAFACE PROTOCOLSPIDOUT MODETDMATAPOSITIONDynamicMlSPITDMFixed010SPIDiscrete11Frame-SyncT口 MDynamic100Frame-SncTDMFixed

15、101Frame-SyncDiscrete=110Modulator Mode5. 供电电压ADS1278需要 3 个电压 DVDDIOVDD和 AVDD其中 DVDDfe压为 1.65-1.95V （当 32.768MHz f CLK 11此电路输入端电容不得小于0.1UF，输出端不得小于2.2uF，NR脚电容不得大于0.01UF。为保证性能，PCB走线时，Vin和Vout的地线层需要单独走线，最后接到器件的GND引脚上。此芯片还可设置可调电压输出，电路如下:OinPl/T VOLTAGE PnOGRAMUiNG QUIQEOUTPUT VOLTAGEfflnaCl1.22 VshortST

16、.eka30.1 h叶 22 pF2.5 V3.1 V511 Ik n30.1 h 灯15pF36 VS9kn301ltl5pFhodiTFS7ii EhhR GND FB其中 Vout=Vref*(1+R1/R2),Vref=1.225V(芯片内部产生）。建议R1=30.1kQ，故有:C,(3X W-丁+ Rj)(R, X R/般 C1可为15pF。AVDD采用TPS73501,因为其有更好的 SPRR和低噪声性能。固定电压电路及可调电压电路如下图所示:Optional input capacitor. May improve source irripGcbance, noise, Or P

17、SRRINOUTTPS73SXXoirrEM GND NR=5 2,2 mFCeramicOVenh -VOplion剖 bypass capacitorto reduce oirtput noiseand increase PSRR.Optional input 匚apacitor.May inriprove source impnco, rtoise, Or PSRR iVm-4-J*%=*INOUTTPS735011-VEN GNO FB二二 2卫 IIFCeramic。Cff 容值为 3pF-1 nF。输入端电容一般为 0.1uF-1uF，低ESR的电容（陶瓷电容最佳）R1 = Vou

18、t * R2 / 1.208-R2;VoutR2R11.830.114.75099530.194.48609电源供电能力要求:冷w difiupallonHqh-R&UlLtftn ifl Low-Pawflf mode 5祚 Spaed mcnie mh Sfiaed nodfl 上坦h RMduTwi mcxhLqw-Pqimv rrode Lcm-Etcrd mode liqh-Socerf n nkXleLum 异说出Hgh-Sp9d node h+fln-Re&oliJton moJa Low-Pch- rnode Lo 小 Spaed moefc够074423t?50 350 1皓

19、01250曲s5t5Z4&50rtlA1+51mAinAiMrr22mA3D|I.ml11745fl占店左76B7653粘rnArnA11*mArrWrrrwrriWrriWilId it - 37MHz max tor Hgli Spead mode, and 27MHz max for Fl otiflr modes. Sea T出& 7 Ta r DVDD reECrictioni lin High-Spew nwov.6. ADS1278电路设计AGN刖DGN可以使用同一个地平面。ADS1278。数字输入脚需要串接 50 Q电阻，并放置在数字驱动源末端（靠近模拟电路（输入脚）走线必须远

20、离数字电路（输入脚）并防止产生走线交叉。模拟信号参考端接10UF和O.luF电容AINP模拟信号输入端必须接 THS4521驱动，P CB走线短而直，且远离数字信号线。和AINN之间须接1-10nF电容。电源、模拟输入、参考输入的去耦电容必须尽可能的靠近ADS1278时钟线越短越好,且末端接 50Q电阻。要求晶振必须稳定。7. 特殊引脚说明SYNC同步引脚。当此引脚输入负向脉冲时,ADS1278被同步。当为低电平时,AD转换停止、数字滤波计数器清零。当为多ADS1278系统时，SYNC引脚用于使多个ADS1278硬件同步。在Frame-Sync模式下时，SYNC为低时，DOUT为零，为了保证

21、正确同步，在 SYNC恢复为高电平时，FSYNC,SCLK,和CLK必须已经建立且保持运行。在ADS1278上电时，须重置 SYNC对应时序如下所示: IpiWJ 5VNCnrSYHCMi_nLr- V- kcsuWIFTFigure 74SynchronlzaUom Timing (Frame-Sync Prolocol)Table 12. IFrame-Sync ProtocolSYMBOLEscfapmoNUINrvpUAXNITSksHpCLK ft SVnC hoW time10tscwSYNC 10 CLK setup tme5rtaIsSynctirwiue pulse vndt

22、hrCLK pencdsNPRfifiie for nw dala la be read/1計1甜Coriversnris (l/foATJ)(11 If SYNC 餾.jyrImnjCOfivei bJOfl pAiiOd (VFoata)?5StcixFsHngor CLK io raving 却 ai ORDv32ns恤區Filing adgs of DHDV lo rising Jgs of lira &CLK to p&lneus data1CCLHmsbpdDRDV laltrig ad驴 to DOUlT MSB vahd Ao|mj沪ion delay)iienfiIscFahng cdflt ct SCLK to nsirtg edge of DRDVIflns滋1SCLK pBriodSCLK posdw Or rvqahfe exm wi(#JiSOL K raiinuto nw DOUT 浪詛灯 昭口 s(ne)10.410tem S识 nsIdopJMSCLK tailing 39 to new DOUT vdlHl prupagation和32in2&HB 3tiBirHew Dlhlahd U) laiing DdgD a SCLK |set