CPLD设计BCD的优先编码器、BCD码十进制加法计数器、8位的左右移位寄存器电路、时钟分配电路、步进马达控制电路

1、1 设计一个bcd的优先编码器电路，输入为10个开关的状态，要求输出开关对应的编码。输出编码用4位表示，第一个开关为0时，输出为0000时，第二个开关为0时，输出为0001时，. 第10个开关为0时，输出为1001。第10个开关的优先级最高。当没有按键按下时，输出信号e为1。有按键按下时，输出信号e为0。1顶层原理图及说明 k0-k9为10个开关，y0-y3为编码输出，其中k9的优先级最高2 每个宏单元如何实现（对所写代码的说明） library ieee;use ieee.std_logic_1164.all;entity encode is/输入输出初始化 port ( k0: in st

2、d_logic; k1: in std_logic; k2: in std_logic; k3: in std_logic; k4: in std_logic; k5: in std_logic; k6: in std_logic; k7: in std_logic; k8: in std_logic; k9: in std_logic; y: out std_logic_vector( 3 downto 0); e: out std_logic );end encode;architecture encode_arch of encode isbegine=k0 and k1 and k2

3、and k3 and k4 and k5 and k6 and k7 and k8 and k9; /如果都是1的话则e为0y=1001 when(k9=0) else /进行优先编码，根据优先级依次判断 1000 when(k9=1 and k8=0) else 0111 when(k9=1 and k8=1 and k7=0) else 0110 when(k9=1 and k8=1 and k7=1 and k6=0 ) else 0101 when(k9=1 and k8=1 and k7=1 and k6=1 and k5=0 ) else 0100 when(k9=1 and k8

4、=1 and k7=1 and k6=1 and k5=1 and k4=0) else 0011 when(k9=1 and k8=1 and k7=1 and k6=1 and k5=1 and k4=1 and k3=0) else 0010 when(k9=1 and k8=1 and k7=1 and k6=1 and k5=1 and k4=1 and k3=1 and k2=0) else 0001 when(k9=1 and k8=1 and k7=1 and k6=1 and k5=1 and k4=1 and k3=1 and k2=1 and k1=0) else 000

5、0 when(k9=1 and k8=1 and k7=1 and k6=1 and k5=1 and k4=1 and k3=1 and k2=1 and k1=1 and k0=0) else xxxx; /若无法确定状态，则输出xxxxend encode_arch;3 时序仿真结果4 时序分析=timing constraint: default period analysis 41 items analyzed, 0 timing errors detected. maximum delay is 13.241ns.=timing constraint: default net en

6、umeration 25 items analyzed, 0 timing errors detected. maximum net delay is 2.435ns.=2 设计一个2位的bcd码十进制加法计数器电路，输入为时钟信号clk，进位输入信号cin，每个bcd码十进制加法计数器的输出信号为d、c、b、a和进位输出信号cout，输入时钟信号clk用固定时钟，进位输入信号cin.1顶层原理图及说明 以第四位计数器的进位段作为高四位的时钟信号，因为设计为到1001b（9）进位输出，所以再输出端加了一个非门，翻转输出，达到延迟一个时钟信号的目的。2 每个宏单元如何实现（对所写代码的说明）li

7、brary ieee;use ieee.std_logic_1164.all;entity bcd is port (/输入输出初始化 cin: in std_logic; clk: in std_logic; r:in std_logic; d: out std_logic; c: out std_logic; b: out std_logic; a: out std_logic; cout: out std_logic );end bcd;architecture bcd_arch of bcd istype statetype is (st0,st1,st2,st3,st4,st5,st

8、6,st7,st8,st9);/共有10个状态signal present_state,next_state :statetype;signal f:std_logic_vector(3 downto 0);beginprocess(clk)beginif(clkevent and clk=1)then/时钟信号上升沿触发if r=1 then/复位信号present_state=st0;/采用多进程的摩尔状态机设计方法elsepresent_state f=0000;cout=0;next_state f=0001;cout=0;next_state f=0010;cout=0;next_s

9、tate f=0011;cout=0;next_state f=0100;cout=0;next_state f=0101;cout=0;next_state f=0110;cout=0;next_state f=0111;cout=0;next_state f=1000;cout=0;next_state f=1001;cout=1;next_state=st0; end case;end process;d=f(3);/把f信号输出到输出端c=f(2);b=f(1);a=f(0);end bcd_arch3 时序仿真结果4 时序分析=timing constraint: default p

10、eriod analysis 91 items analyzed, 0 timing errors detected. minimum period is 4.878ns. maximum delay is 12.324ns.=timing constraint: default net enumeration 33 items analyzed, 0 timing errors detected. maximum net delay is 2.540ns.-3 设计一个8位的左右移位寄存器电路，输入为时钟信号clk，方向控制信号d，输出信号为每个寄存器的状态1顶层原理图及说明 clk为时钟信

11、号，d为方向控制信号，r为复位信号，s0-s9为状态输出2 每个宏单元如何实现library ieee;use ieee.std_logic_1164.all;entity displace is port (/输入输出初始化 d: in std_logic; r: in std_logic; clk: in std_logic; s: out std_logic_vector(7 downto 0) );end displace;architecture displace_arch of displace istype statetype is (st0,st1,st2,st3,st4,st

12、5,st6,st7);/共有8个状态，非别对应8个移位输出signal present_state,next_state :statetype;beginprocess(clk)beginif(clkevent and clk=1)then/时钟信号上升沿触发if r=1 then/复位信号present_state=st0;/采用多进程的摩尔状态机设计方法elsepresent_state s=10000000; if d=1 then next_state=st1;/d信号控制方向 else next_state s=01000000; if d=1 then next_state =st

13、2; else next_state s=00100000; if d=1 then next_state=st3; else next_state s=00010000; if d=1 then next_state=st4; else next_state s=00001000; if d=1 then next_state=st5; else next_state s=00000100; if d=1 then next_state=st6; else next_state s=00000010; if d=1 then next_state=st7; else next_state s

14、=00000001; if d=1 then next_state=st0; else next_state=st6; end if; end case;end process; end displace_arch;3 时序仿真结果4 时序分析=timing constraint: default period analysis 48 items analyzed, 0 timing errors detected. minimum period is 4.881ns. maximum delay is 9.065ns.=timing constraint: default net enume

15、ration 11 items analyzed, 0 timing errors detected. maximum net delay is 2.556ns.-4 设计一个时钟分配电路，输入为时钟信号clk，输出为信号f0f5，这六个信号中只允许有一个为高电平，f0、f2、f4的持续时间为2个clk，f1、f3、f5的持续时间为4个clk。1顶层原理图及说明 r为复位信号，clk为时钟信号，f0-f5为输出信号每个宏单元如何实现library ieee;use ieee.std_logic_1164.all;entity divide is port (/输入输出初始化 r: in std

16、_logic; clk: in std_logic; f: out std_logic_vector(5 downto 0) );end divide;architecture divide_arch of divide istype statetype is (st0,st1,st2,st3,st4,st5,st6,st7,st8);/共9个状态，分别对应相应的输出signal present_state,next_state :statetype;signal clkss:std_logic;beginprocess(clk)beginif(clkevent and clk=1)then/

17、clk上升沿触发clkss=not(clkss); /把两个clk上升沿转化成一个clkss上升沿end if;end process;process(clkss)beginif(clkssevent and clkss=1)thenif r=1 then/clkss上升沿触发present_state=st0;/采用多进程的摩尔状态机设计方法elsepresent_state f=100000;next_state f=010000;next_state f=010000;next_state f=001000;next_state f=000100;next_state f=000100;

18、next_state f=000010;next_state f=000001;next_state f=000001;next_state=st0; end case;end process; end divide_arch;3 时序仿真结果4 时序分析=timing constraint: default period analysis 36 items analyzed, 0 timing errors detected. minimum period is 4.236ns. maximum delay is 10.437ns.=timing constraint: default ne

19、t enumeration 14 items analyzed, 0 timing errors detected. maximum net delay is 2.386ns.-5 设计一个状态机电路，驱动步进马达的四相控制线圈a、b、c、d。马达向前的四相控制线圈通电过程为：a-ab-b-bc-c-cd-d-da-a,后退的过程为a-da-d-dc -c-bc-b-ab-a,输入时钟信号clk和dir方向控制端控制马达的前进和后退。1顶层原理图及说明 dir为方向信号，r为复位信号，clk为时钟信号，abcd为输出信号2 每个宏单元如何实现library ieee;use ieee.std_

20、logic_1164.all;entity moto is port ( dir: in std_logic; r: in std_logic; clk: in std_logic; a: out std_logic; b: out std_logic; c: out std_logic; d: out std_logic );end moto;architecture moto_arch of moto istype statetype is (st0,st1,st2,st3,st4,st5,st6,st7);/共八个状态对应相应的输出signal present_state,next_state :statetype;signal s:std_logic_vector(0 to 3);beginprocess(clk)beginif(clkevent and clk=1)then /上升沿触发if r=1 thenpresent_state=st0;elsepresent_state s=1000; if dir=1 then next_state=st1;/dir信号控制方向 else next_state s=1100; if dir=1 then next_state =st2; else next_