vhdl语言实验报告

1、 电了设计自动化 多路波形发生器 指导老师：刘彪 电气工程学院 电气1003班 杨黎 10291094 2012年10月27日 一、实验题目要求 1、对输入时钟信号进行分频，实现三路互差120 的信号。 2、实现输出信号的占空比控制 clk: 输入时钟信号 reset: 同步复位信号(低电平有效) div: 输入分频控制信号 (注意： 6n 分频 ) ctrl: 占空比控制信号 ctrl=1 时 , 占空比为 1:1 ctrl=2 时 , 占空比为 1:2 ctrl=3 时 , 占空比为 2:1 A,B,C: 三路输出信号 二、设计思路及方案 1、多路发生器的基本原理分频器而且是可调的。因此可

2、以先设计多个子程序分别使得信 号发生器的产生的占空比分别为 1:1,1:2,2:1 ；因此先设 div:integer range 1 to 4; 。通过信号 赋值( tmp,tmp1,tmp2 )赋给输出信号 A,B,C. 通过 n 改变输出频率。定义各个变量。 2、当 resetb=O 时,countQ=O ; 当 resetb=1 时。给脉冲时先定义分频比如果 countQ (6*div-1) 时 countQ= countQ 否则 countQ 为 0。 3、当 cltr=01 时即 H:L=1:1 时 如果 countQ 3*div 时 tmp= 0 ;否者 tmp=1 如果 cou

3、ntQ(6*div-2) 时 tmp1= 1; 否者 tmp1=0; 如果 countQ(4*div-1) 时 tmp2= 0; 否者 tmp2=1; A 等于 tmp； B=tmp2； C=tmp3 ； 同理：当 cltr=10 时即 H:L=1:2 时 当 cltr=11 时即 H:L=2:1 时。 其中；公式推导如下： 当 div=1,cltr=01 时当 div=2， cltr=01 时 countQ6 A：0 0 0 1 1 1； countQ12 A:0 0 0 0 0 0 1 1 1 1 1 1 B:1 1 1 1 0 0 0 0 0 0 1 1 C:0 0 1 1 1 1 1

4、1 0 0 0 0 A； countQ6 时 tmp=0 Else tmp=1 countQ10 ，tmp=1 B：1 1 0 0 0 1； C：0 1 1 1 0 0； A： countQ3 时 tmp=0 Else tmp=1 B： countQ4 时 tmp=1 B： Else tmp=0Else tmp=0 C:countQ3 时 tmp=0 C: countQ7 时 tmp=0 Else tmp=1Else tmp=1 同理： cltr=10 ， cltr=11. 当 cltr=01 时 if(countQ 3*div) then tmp= 0;else tmp=1; if(coun

5、tQ(6*div-2) then tmp1= 1;else tmp1=0： if(countQ(4*div-1) then tmp2= 0;else tmp2=1; 当 cltr=10 时 if(countQ 4*div) then tmp= 0;else tmp=1; if(countQ 2*div ) then tmp1= 1;else tmp1=0; if(countQ(4*div-1) then tmp2= O; else tmp2=1; 当 cltr=11 时 if(countQ 2*div) then tmp= O;else tmp=1; if(countQ(4*div-1) th

6、en tmp1= 1;else tmp1=0; if(countQ 4*div ) then tmp2= 1;else tmp2=0; 将信号tmp赋给A ; tmpl赋给B ; tmp2赋给 C ; 三、流程图 Reset=0? 四、实验程序及其波形 libraryieee; use ieee.std_logic_1164.all; useieee.std_logic_arith.all; useieee.std_logic_ un sig ned.all; en tityfashe ngq is port ( clk:i nstdo gic; aclk:outstdo gic; bclk:

7、outstdo gic; cclk:outstd_logic; resetb:instd_logic; div:instd_logic_vector(1 downto 0); ctrl:instd_logic_vector(1 downto 0) ); endfangshengq; architecture behave of fangshengq is signaltmp:std_logic; signal tmp1:std_logic; signal tmp2:std_logic; signal cnt0:integer range 0 to 5:=0; signal cnt1:integ

8、er range 0 to 11:=0; signal cnt2:integer range 0 to 17:=0; signal cnt3:integer range 0 to 23:=0; begin process(clk,resetb,div,ctrl) begin if clkevent and clk=1 then ifresetb=0 then cnt0=0; cnt1=0; cnt2=0; cnt3=0; tmp=0; tmp1=0; tmp2=0; elsifresetb=1 then cnt0=cnt0+1; cnt1=cnt1+1; cnt2=cnt2+1; cnt3 c

9、ase div is when 00= case cnt0 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2=0;cnt0 case cnt1 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=

10、0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt1 case cnt2 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=

11、0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt2 case cnt3 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=

12、0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt3 case div is when 00= case cnt0 is when 0=tmp=0;t

13、mp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2=0;cnt0 case cnt1 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;t

14、mp1=0;tmp2tmp=1;tmp1=0;tmp2=0;cnt1 case cnt2 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;t

15、mp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2=0;cnt2 case cnt3 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;t

16、mp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2=0;cnt3 case div is when 00= case cnt0 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp

17、=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt0 case cnt1 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt1 case cnt2 is

18、 when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp

19、=1;tmp1=1;tmp2=0;cnt2 case cnt3 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp

20、=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt3tmp=0;tmp1=0;tmp2=0; end case; end if; end if; end process; aclk=tmp; bclk=tmp1; cclk=tmp2; end behave; 实验波形如下图所示: 【1】 i.J SuMw ElNstn Flow 名mn

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