数字接收的外文翻译.pdf

1 西西 安安 邮邮 电电 大大 学学 毕毕 业业 设设 计 计 译译 文 文 论文题目 论文题目 基于多相滤波器组及瞬时测频技术的高效 带宽数字接收机研究 院院 系 系 通信与信息工程学院通信与信息工程学院 专专业 业 电子信息科学与技术电子信息科学与技术 班班级 级 电科电科 0903090309030903 班班 学生姓名 学生姓名 李盼李盼 导师姓名 导师姓名 常虹常虹职称 职称 讲师讲师 2 A A A ACOMPARISONCOMPARISONCOMPARISONCOMPARISON OFOFOFOF ANALOGANALOGANALOGANALOGFRONTFRONTFRONTFRONT ENDENDENDEND ARCHITECTURESARCHITECTURESARCHITECTURESARCHITECTURES FORFORFORFORDIGITALDIGITALDIGITALDIGITAL RECEIVERSRECEIVERSRECEIVERSRECEIVERS HollyHollyHollyHolly PekauPekauPekauPekauStudentStudentStudentStudent Member Member Member Member IEEE IEEE IEEE IEEE UniversityUniversityUniversityUniversity ofofofofCalgaryCalgaryCalgaryCalgaryTRLabsTRLabsTRLabsTRLabs e mail pekau atips cae mail pekau atips cae mail pekau atips cae mail pekau atips ca JamesJamesJamesJames W W W W HaslettHaslettHaslettHaslettFellow Fellow Fellow Fellow IEEE IEEE IEEE IEEE UniversityUniversityUniversityUniversity ofofofofCalgaryCalgaryCalgaryCalgaryTRLabsTRLabsTRLabsTRLabs e mail e mail e mail e mail haslett enel ucalgary cahaslett enel ucalgary cahaslett enel ucalgary cahaslett enel ucalgary ca AbstractAbstractAbstractAbstract Radio receivers that perform analog to digital conversion closerto the antenna and do most of the signal processing in the digital domain are known as digital receivers Digital receivers aredesirable because they can be more easilyre configured for multista dard operation they can facilitate performance improvementsby using digitalfilters for signal processing and they can potentia llyrealize savings in chip area power consumption and cost The definition of a digital receiverisgeneral and there are several types of receiver architectures thatfallinto this category Digitalreceiver architectures which have been proposed include direct RFNyquist sampling RF bandpass sampling or sub sampling directIF Nyquist sampling and IF bandpass sampling orsubsamp ling This paper compares these digital receiver architecturesinvarious categories including susceptibility to aperture jitter and aperturedistortion noisefigure degradation due to aliasing easeofanti aliasing filter implementation ease of ADC implemen tation linearity power consumption chip area and re configurability System and circuit level simulations using a commercial RF simulator are performed to quantitatively compare the different digital receiver architectures in some of theaforementionedcategories Thefeasibilityof usingtheproposeddigitalreceiver architectures forvarious standardsisthen examined and a survey of published digital receiver architecturesispresented Keywords Digital receiver software radio sub sam 3 1 1 1 1IntroductionIntroductionIntroductionIntroduction The increasing demand forflexible multi standard multi bandradios increases and recent improvements in analog to digital converter technology have led to the developmentof software radios with digital receivers In a software radio receiver wideband analog to digital conversion that captures multiple channels of thesoftware radio nodeisperformed closer to the antenna In addition to the improvedflexibilityofusewith multiple standards overmultiple frequency bands digital receivers offer potential savings in power consumption circuit area and cost and can potentially realize performance improvements resulting from the use of digitalfilters The definitionofa digital or software receiverisgeneral and encompasses numerous architectures with various types of analog front ends These architectures include direct RF sampling RF sub sampling IF sampling and IF sub sampling The block diagram ofanRF sampling or sub sampling receiverisshown in Figure 1 RF Sampling or sub sampling receiver block diagram Figure 2 IF Sampling or sub sampling receiver block diagram Fig 1 and the block diagram ofanIF sampling or sub samplingreceiverisshown inFig 2 4 In an RF or IF sampling receiver samplingisdone at at least twice the maximum RF or IF frequency resulting in a sampled output at the RF or IF frequency In an RF or IF sub sampling receiver samplingisdone at at least twice the RF or IF bandwidth resultingis an aliased sampled output around multiples of the sampling frequency as shown in Fig 3 a There may be additional restrictions on the sampling frequency to avoid aliasing in the case of sub sampling as described by Vaughan in 1 In this work we compare the different digital receiver architectures with respect to their susceptibility to aperture jitter and aperture distortion noisefigure degradation due to aliasing ease of anti aliasingfilterimplementation ease of ADC implementation linearity power consumption chip area and re configurability Figure 3 Results of sub sampling a Aliasing of signal band to Nyquist band b Noise aliasing to Nyquist band c Noise aliasing when inputisbandpassfiltered prior to sub sampling 2 2 2 2SusceptibilitySusceptibilitySusceptibilitySusceptibility totototo ClockClockClockClock ApertureApertureApertureAperture JitterJitterJitterJitter Aperture jitter or the sample to sample variation of the sampling instant relative to an ideal clock causes the signal to noise ratio SNR ofan ideal sampling system given to be 2 10 20log2 ajrms SNRf t 1 5 where faisthe input signal frequency being sampled and tjrmsisthe rms jitter The above expressionisan approximation basedonthe assumption that the input signalis sinusoidal and that the timing jitter has zero mean A more generic formofthe expression for the SNR in terms of the autocorrelations of the sampled signal and the timing jitterisgiven by Da Dalt in 2 but for this work the approximate expressionismore useful asitisa function of known parameters The effective numberofbits ENOB foranADCislimited by the signal to noise and distortion ratio SINAD andisgivenby 1 76 6 02ENOBSINADdbB 2 Using the preceding expression and equation 1 the maximum achievable ADC resolution foranideal ADC where SNRislimitedonlyby aperture jitter can be plotted versus input frequency for several clock jitter values as shown in Fig 4 Aperture jittercancause additional performance degradation in sub sampling systems 3 Jitter affects frequencies in the sampled signal spectrum that are aliased to the frequency band of interestbutthis effect can be mitigatedbyadequate anti aliasingfiltering Additional jitter requirements in sub sampling systems are imposedbythe frequency being sampled and the signal bandwidth as discussed by Vaughanin 1 The jitter requirements imposed bythe sub sampling process become more stringent as the frequency being sampled increases but are independentofthe jitter requirements imposed by the required ADC resolution Figure 4 Number of ADC bits versus aperture jitter Despite the SNR degradation caused by clock jitter in both direct RF sampling and RF sub sampling and the jitter requirements imposedbythe sampling frequency limitations in RF sub sampling receivers using both types of RF sampling have been implemented for standards that do not require veryhighADC resolution Current state of theartcommercial 6 PLLs can achieve 0 25ps rms jitterat 800MHz This low jitter would allow 12 bit analog to digital conversion to be done at 800MHz 3 3 3 3ApertureApertureApertureAperture DistortionDistortionDistortionDistortion At the sampling instant the transition of control signals from track to hold causes distortion in the sampled signal The distortion can occur through a number of mechanisms that are dependentonthe clock signal transition time the signal characteristics the sampling circuit architecture the device geometries and the fabrication technology The distortion increases with input frequency imposing stricter requirementsonsampling switches and clock generation circuits as the frequency being sampled increases The increase in distortion with frequency being sampledisdifficult to quantify becauseitdepends on multiple factors but several authors have quantified thetotalharmonic distortion caused by sample andhold settlingtimefor specific sampling architectures 4 5 Required clock transition times are also dependent on the specific sampling architecture used the maximum input frequency and the required ADC resolution 4 4 4 4NoiseNoiseNoiseNoise FigureFigureFigureFigure DegradationDegradationDegradationDegradation duedueduedue totototoAliasingAliasingAliasingAliasing andEaseandEaseandEaseandEase ofofofof Anti aliasingAnti aliasingAnti aliasingAnti aliasing FilterFilterFilterFilter ImplementationImplementationImplementationImplementation In a sampling system noiseisfolded from multiplesofthe sampling frequency to the Nyquist band as shown in Fig 3 b In order to reduce the noise folded to the Nyquist band from multiplesoffs the signalisusually bandpassfiltered before sub sampling as shown in Fig 3 c As the ratio of the sampling frequency to the maximum frequency being sampledis decreased the potential amount of noise aliasingisincreased and the requirements of the anti aliasingfilter are increased As the anti aliasingfilter requirements are increased they become more difficult to design and to integrate on chip The design ofhighquality on chip filters at RF 7 Figure5 Sampled output spectrum of an RF sampling receiver fRF 2 42GHz fs 5GHz frequenciesisvery difficult andisstill an active area of research though advancements in Q enhanced LCfilters and in MEMs devices are making the realizationofsuchfilters more feasible 5 5 5 5EaseEaseEaseEase ofofofof ADCADCADCADC ImplementationImplementationImplementationImplementation Speed limitations in the design of ADCs makeitdifficult to perform analog to digital conversion at RF frequencies especially athighresolutions These speed limitations are due to the inherent speed limitations of the transistors used to design the ADC s and to the increase in power and area thatisneeded to achieve high resolution athighfrequencies Therefore in the case ofanRF sampling receiver where A D conversion withsufficient resolution cannot be done at the RF frequency discrete timefiltering and decimationisdone prior to A D conversion as described in 6 6 6 6 6LinearityLinearityLinearityLinearity In addition to the usual second and third order intermodulation products that cause distortion in receivers RF and IF sampling receivers are sensitive to distortion due to aliasing Aliasing causes distortion products in the sampler input spectrum to appear in the Nyquist spectrum andisespecially difficult to mitigateinthe case of sub sampling where the number of frequencies that alias to the Nyquist bandisdrastically increased Figures 5 and 6 show the output spectra of an RF sampling andanRF sub sampling receiver The increased numberof tones due to aliasing in the spectrum of the RF sub sampling receiverisevident Due to the effects of aliasing sub sampling receivers generally have poorer linearity and more stringent anti aliasingfilter requirements than Nyquist sampling receivers but this degradation in linearity may be difficult to capture usingfigures of merit such as third order intercept IP3 which are geared to receiver front ends which do not perform sampling RF sampling and sub sampling receivers may suffer from distortion problems because allthe gainisrealized at the RF frequency andhighgain with good linearityisgenerally more difficult to achieve athighfrequency due to the increased effect of parasitics 8 Figure 6 Sampled output spectrum ofanRF sub sampling receiver fRF 2 42GHz fs 100M Hz and the lower intrinsic gain of transistors at high frequencies IF sampling and sub sampling receivers may have degraded distortion performance compared to RF sampling receivers due to the use of a mixer which may introduce additional distortion products 7 7 7 7PowerPowerPowerPower Consumption Consumption Consumption Consumption CircuitCircuitCircuitCircuit Complexity Complexity Complexity Complexity ChipChipChipChip AreaAreaAreaArea andandandand ReconReconReconReconfi fi fi figurabilitygurabilitygurabilitygurability The analog receiver front end power consumption circuit complexity and chip area of an RF sampling receiver are generally less than those ofanIF sampling receiver because fewer circuit blocks are used However differentfilter implementations at RF and IF frequencies may require very different amounts of chip area and consume different amounts of current so the comparison depends strongly on the design of the circuit blocks comprising the receiver The power consumption of a complete RF sampling receiver including the digital base band may be higher than that ofanIF sampling receiver due to the high power consumption ofvery high frequency digital signal processing This problem may be mitigated by discrete time filtering and decimating the sampled RF signal before A D conversion but this adds circuit complexity RF sampling receivers are generally more re configurable for multi standard use than IF sampling receivers because they contain a smaller number of analog circuit blocks which are typically less configurable than digital circuits 8 8 8 8SimulationSimulationSimulationSimulation ResultsResultsResultsResults Twelve sampling receiver architectures with an RF frequency of 2 42GHz were 9 simulated using a commercial RF simulator Three direct RF sampling and three RF sub sampling architectures as showninFig 1 were designed with different anti aliasingfilters with S21 responses shown inFig 7 and a sampling frequency of 5GHz for the direct sampling architectures and 100MHz for the sub sampling architectures Three direct IF samplingand three IF sub sampling architectures were also designed with different antialiasingfilters with S21 responses shown in Fig 8 anIF frequency Figure 7 S21ofRF bandpassfilters used in RF and IF sampling receivers Figure 8 S21of IF anti aliasingfilters used in IF sampling receivers of 100MHz and sampling frequencies of 240MHz for the direct sampling architectures and 80MHz for the sub sampling architectures The architecture of the IF sampling and sub sampling receiversisshown in Fig 2 butthe RF bandpassfilters used for the three RF sampling receivers wereleftin place to further reduce noise aliasing and distortion The same LNA with 28 dB of gain and the same sampler with 10dB of gain are used forallarchitectures The same mixer with 0dB ofgainisused forallthe IF sampling and sub sampling 10 architectures Allfilters were implemented as ideal lumped element LC topologies Simulation results for the receivers are given in Table I Itcan be seen that the noise performance of the sub sampling architecturesis consistently worse than that of the direct sampling architectures due to the effects of noise aliasing The IF sampling architectures have lower noisefigures than the RF sampling architectures despite theuseof a noisy mixer probably because two anti aliasingfilters are used in the IF sampling architectures The linearity and power consumptionofthe RF sampling architectures are better because a mixerisnot used The output SNR and equivalent maximum A D converter resolution in bits including the effectsofa 1ps aperture jitter are calculated using the simulated noisefigure and equation 1 Itcanbe seen that aperture jitter dominates the noise performance of the RF sampling and RF sub sampling receivers 9 9 9 9SurveySurveySurveySurvey ofofofof PublishedPublishedPublishedPublished RFRFRFRF andandandand IFIFIFIF SamplingSamplingSamplingSampling ReceiversReceiversReceiversReceivers TableIIshows the sampled RF or IF and sampling frequencies of recent published RF and IF sampling receivers for various standards Itcan be seen that IF sampling and sub sampling receivers have been used for some of the more stringent radio standards such as GSM EDGE and WCDMA whereas RF sampling and sub sampling architectures have been limited to applications such as Bluetooth radar GPS and certain WLAN applications with less stringent standards TABLEI SIMULATED PERFORMANCE OF RF AND IF SAMPLING AND SUB SAMPLING RECEIVERS fs SAMPLING FREQUENCY ArchitectureFiltersRF IF MHz fs MHz Gain dB NF dB ADC SNR ENOB dB IIP3 dB OP1dB dB IDC mA RF Sampling RF Sampling RF Sampling RF Sub sampling RF Sub sampling RF Sub sampling RF1 RF2 RF3 RF1 RF2 RF3 2420 2420 2420 2420 2420 2420 5000 5000 5000 100 100 100 38 38 3 38 3 38 38 3 38 3 4 4 11 8 12 5 6 6 16 5 20 1 31 7 5 0 31 7 5 0 31 7 5 0 31 7 5 0 31 7 5 0 31 7 5 0 27 26 9 26 34 6 35 3 35 7 5 5 5 5 5 5 17 17 17 17 17 17 IF Sampling IF Sampling IF Sampling IF Sub sampling IF Sub sampling IF Sub sampling RF1 IF1 RF2IF2 RF3 IF3 RF1 IF1 RF2 IF2 RF3 IF3 2420 100 2420 100 2420 100 2420 100 2420 100 2420 100 240 240 240 80 80 80 36 6 38 37 8 36 6 38 37 8 3 19 11 2 16 0 4 1 14 0 22 5 73 3 11 9 63 7 10 3 60 4 9 8 71 4 11 6 62 1 10 0 52 5 8 4 41 6 41 5 40 7 33 3 36 9 39 5 0 0 0 0 0 0 23 23 23 23 23 23 11 IF MHz fs MHz Standard Modulation TypePublication 290 170 650 450 377 69 12 900 1 25 50 1600 2400 800 1500 40 40 40 40 52 30 72 45 6 25 27 73 45 4 8 800 3000 WLAN QPSK WLAN 16QAM WCDMA QPSK WCDMA 16QAM GSM GSM EDGE and WCDMA 802 15 4 GSM EDGE IS 95 CDMA European DVB T GPS Bluetooth WLAN 16 QAM UHFRadar Kiyono 2004 7 Kiyono 2004 7 Kiyono 2004 7 Kiyono 2004 7 Levantino 2003 8 Li2004 9 DeVries 2004 10 Dodley 2000 11 Makowitz 2000 12 Thor2002 13 Muhammad 2004 6 Pekau 2004 14 Song 1997 15 TABLEII RECENT PUBLISHED RF AND IF SAMPLING RECEIVERS fs SAMPLING FREQUENCY 10101010ConclusionConclusionConclusionConclusion RF sampling RF sub sampling IF sampling and IF subsampling receivers have been compared with respect to their sus ceptibility to aperture jitter and aperture distortion noise figure degradation due to aliasing ease of anti aliasingfilter implementation ease of ADC implementation linearity powerconsumption chiparea andreconfigurability Key performance metrics of twelve different sampling receiver architectures were simulated and compared and a survey of published sampling receiver architectures was done IF sampling architectures currently demonstrate better performance than RF sampling architectures due to their lower susceptibility to aperture jitter and the fact that anti aliasingfilters and A