FPGA时钟倍频分频DCM_IP CORE(源码及仿真图).docx

module tb_test;/ Inputsreg CLK_IN1;reg RESET;/ Outputswire CLK_OUT1;wire LOCKED;/ Instantiate the Unit Under Test (UUT)s6_clock uut (.CLK_IN1(CLK_IN1), .CLK_OUT1(CLK_OUT1), .RESET(RESET), .LOCKED(LOCKED);initial begin/ Initialize Inputs/RESET = 0;/ Wait 100 ns for global reset to finish/#100; CLK_IN1 = 0;/ Add stimulus hereRESET = 1;#60RESET = 0;forever begin #20CLK_IN1=!CLK_IN1 ;endend endmoduletimescale 1ps/1ps(/ Clock in ports input CLK_IN1, / Clock out ports output CLK_OUT1, / Status and control signals input RESET, output LOCKED ); / Input buffering /- IBUFG clkin1_buf (.O (clkin1), .I (CLK_IN1); / Clocking primitive /- / Instantiation of the DCM primitive / * Unused inputs are tied off / * Unused outputs are labeled unused wire psdone_unused; wire locked_int; wire 7:0 status_int; wire clkfb; wire clk2x; DCM_SP #(.CLKDV_DIVIDE (2.000), .CLKFX_DIVIDE (1), .CLKFX_MULTIPLY (4), .CLKIN_DIVIDE_BY_2 (FALSE), .CLKIN_PERIOD (20.0), .CLKOUT_PHASE_SHIFT (NONE), .CLK_FEEDBACK (2X), .DESKEW_ADJUST (SYSTEM_SYNCHRONOUS), .PHASE_SHIFT (0), .STARTUP_WAIT (FALSE) dcm_sp_inst / Input clock (.CLKIN (clkin1), .CLKFB (clkfb), / Output clocks .CLK0 (), .CLK90 (), .CLK180 (), .CLK270 (), .CLK2X (clk2x), .CLK2X180 (), .CLKFX (), .CLKFX180 (), .CLKDV (), / Ports for dynamic phase shift .PSCLK (1b0), .PSEN (1b0), .PSINCDEC (1b0), .PSDONE (), / Other control and status signals .LOCKED (locked_int), .STATUS (status_int), .RST (RESET), / Unused pin- tie low .DSSEN (1b0); assign LOCKED = locked_int; / Output buffering /-