how to get the best adc accuracy in stm32

1、AN2834Application noteHow to get the best ADC accuracy in STM32 microcontrollersIntroductionSTM32 microcontrollers embed up to four advanced 12-bit ADCs (depending on the device). A self-calibration feature is provided to enhance ADC accuracy versus environmental condition changes.In applications in

2、volving analog-to-digital conversion, ADC accuracy has an impact on the overall system quality and efficiency. To improve this accuracy, the errors associated with the ADC and the parameters affecting them must be understood.ADC accuracy does not only depend on ADC performance and features, but also

3、 on the overall application design around the ADC.This application note aim is to help understand ADC errors and explain how to enhance ADC accuracy. It is divided into three main parts:a simplified description of ADC internal structure to help understand ADC operation and related ADC parametersexpl

4、anations of the different types and sources of ADC errors related to the ADC design and to external ADC parameters such as the external hardware designrecommendations on how to minimize these errors, focusing on hardware and software methodsFebruary 2017DocID15067 Rev 31/49ContentsAN2834Co

5、ntents1ADC internal principle61.1SAR ADC internal structure62ADC errors102.1Errors due to the ADC itself..42.1.5Offset error10Gain error12Differential linearity error13Integral linearity error14Total unadjusted error162.2Errors due to the ADC environment..42.2.5

6、...11Reference voltage noise17Reference voltage / power supply regulation17External reference voltage parameters18Analog input signal noise18ADC dynamic range bad match for maximum input signal amplitude18Effect of the analog signal source resistance18Effect of source capa

7、citance and parasitic capacitance of the PCB19Injection current effect20Temperature influence20I/O pin crosstalk21EMI-induced noise213How to get the best ADC accuracy223.13.2Reduce the effects of ADC-related ADC errors22Minimize ADC errors related to external environment of ADC..4

8、..8Reference voltage / Power supply noise minimization22Reference voltage / Power-supply regulation24Analog-input signal noise elimination24Adding white noise or triangular sweep to improve resolution25Matching the ADC dynamic range to the maximum signal amplitude26Analog source res

9、istance calculation28Source frequency condition vs. source and parasitic capacitors30Temperature-effect compensation312/49DocID15067 Rev 3AN2834Contents..123.2.13Minimizing injection current31Minimizing I/O pin crosstalk31EMI-induced noise reduction32PCB layout recommendations33Co

10、mponent placement and routing353.3Software methods to improve precision3..43.3.5Averaging samples35Digital signal filtering36FFT for AC measurement37ADC calibration38Minimizing internal CPU noise383.4High impedance source measurement3..4ADC input stage problem39Ex

11、planation of the behavior40Minimizing additional errors41Source of described problem - ADC design454Conclusion475Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48DocID15067 Rev 33/49List of tablesAN2834List of tablesTable 1.Document revision his

12、tory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484/49DocID15067 Rev 3AN2834List of figuresList of figuresFigure 1.Figure 2.Figure 3.Figure 4.Figure 5.Figure 6.Figure 7.Figure 8.Figure 9.Figure 10.Figure 11.Figure 12.Figure 13.Figure 14.Figure 15

13、.Figure 16.Figure 17.Figure 18.Figure 19.Figure 20.Figure 21.Figure 22.Figure 23.Figure 24.Figure 25.Figure 26.Figure 27.Figure 28.Figure 29.Figure 30.Figure 31.Figure 32.Figure 33.Figure 34.Figure 35.Figure 36.Figure 37.Figure 38.Figure 39.Basic schematic of SAR switched-capacitor ADC (example of 1

14、0-bit ADC)6Sample state7Hold state7Step 1: Compare with VREF/28Step 2: If MSB = 0, then compare with VREF8Step 2: If MSB = 1, then compare with VREF9Positive offset error representation11Negative offset error representation11Positive gain error representation12Negative gain error representation13Dif

15、ferential linearity error representation14Integral linearity error representation15Total unadjusted error16Input signal amplitude vs. ADC dynamic range18Analog signal source resistance effect19Analog input with RAIN, CAIN and Cp20Effect of injection current20Crosstalk between I/O pins21EMI sources21

16、Power supply and reference decoupling for 100- and 144-pin packages23Power supply decoupling for 36-, 48- and 64-pin packages23Simple quasi-triangular source using a microcontroller output25Selecting the reference voltage26Preamplification27Worst case error: VAIN = VREF+28Recommended values for RAIN

17、 and CAIN vs. source frequency FAIN30Crosstalk between I/O pins31Shielding technique32Separating the analog and digital layouts33Separating the analog and digital supplies34Typical voltage source connection to ADC input39Noise observed on ADC input pin during ADC conversions39ADC simplified schemati

18、c of input stage - sample and hold circuit40ADC input pin noise spikes from internal charge during sampling process40Effect of sampling time extension41Charging the external capacitor with too short time between conversions42Implementation of sampling switch45Parasitic capacitances of sampling switc

19、h46Parasitic current example inside ADC structure46DocID15067 Rev 35/49ADC internal principleAN28341ADC internal principle1.1SAR ADC internal structureThe ADC embedded in STM32 microcontrollers uses the SAR (successive approximation register) principle, by which the conversion is performed in severa

20、l steps. The number of conversion steps is equal to the number of bits in the ADC converter. Each step is driven by the ADC clock. Each ADC clock produces one bit from result to output. The ADC internal design is based on the switched-capacitor technique.The following figures (Figure 1 to Figure 6)

21、explain the principle of ADC operation. The example given below shows only the first steps of approximation but the process continues till the LSB is reached.Figure 1. Basic schematic of SAR switched-capacitor ADC (example of 10-bit ADC)1. Basic ADC schematic with digital output.6/49DocID15067 Rev 3

22、9,195()6D66666666666&6E$ 354$& DWD&/.&/5$& &ONAN2834ADC internal principleFigure 2. Sample state1.Sample state: capacitors are charging to VIN voltage. Sa switched to VIN, Sb switch closed during sampling time.Figure 3. Hold state1.Hold state: the input is disconnected, capacitors hold input voltage

23、. Sb switch is open, then S1-S11 switched to ground and Sa switched to VREF.DocID15067 Rev 37/4995()9,16D66666666666& & & &6E$ 354 $& DWD &/.&/5$& &ON9&203 9,1&(TXLYDOHQW FLUFXLW$ DL E95()9,16D66666666666& & & &6E$ 354 $& DWD &/.&/5$& &ON9&2039,1&(TXLYDOHQW$ FLUFXLWADC internal principleAN2834Figure

24、 4. Step 1: Compare with VREF/21.First approximation step. S1 switched to VREF.Figure 5. Step 2: If MSB = 0, then compare with VREF1.Compare with VREF; if MSB =1. S1 switched back to ground. S2 switched to VREF.8/49DocID15067 Rev 395()9,16D66666666666& & & &6E$ 35 4 $& DWD &/.&/5$& &ON9&203 9,1 95()

25、95()&(TXLYDOHQW&$ FLUFXLWDL E95()9,16D66666666666& & & &6E$ 354 $& DWD &/.&/5$& &ON95() &9&203 9,1 95()(TXLYDOHQW&$ FLUFXLWDL EAN2834ADC internal principleFigure 6. Step 2: If MSB = 1, then compare with VREF1.Compare with VREF; if MSB =0. S1 remained switched to ground. S2 switched to VREF.DocID1506

26、7 Rev 39/4995()9,16D66666666666& & & &6E$ 354 $& DWD &/.&/5$& &ON9&203 9,1 95()95()&$(TXLYDOHQW&FLUFXLWDL EADC errorsAN28342ADC errorsThis section lists the main errors that have an effect on A/D conversion accuracy. These types of errors occur in all A/D converters and conversion quality depends on

27、 their elimination. These error values are specified in the ADC characteristics section of the STM32 microcontroller datasheets.Different accuracy error types are specified for the STM32 ADC. For easy reference, accuracy errors are expressed as multiples of 1 LSB. The resolution in terms of voltage

28、depends on the reference voltage. The error in terms of voltage is calculated by multiplyingthe number of LSBs by the voltage corresponding to 1 LSB (1 LSB = VREF+/212 orVDDA/212).2.1Errors due to the ADC itself2.1.1Offset errorThe offset error is the deviation between the first actual transition an

29、d the first ideal transition. The first transition occurs when the digital ADC output changes from 0 to 1. Ideally, when the analog input ranges between 0.5 LSB and 1.5 LSB, the digital output should be 1. Still ideally, the first transition occurs at 0.5 LSB. The offset error is denoted by EO. The

30、offset error can easily be calibrated by the application firmware.ExampleFor the STM32 ADC, the smallest detectable incremental change in voltage is expressed in terms of LSBs:1 LSB = VREF+/4096 (on some packages, VREF+ = VDDA).If VREF+ = 3.3 V, the input of 402.8 V (0.5 LSB = 0.5 805.6 V) should id

31、eally lead to the generation of a digital output of 1. In practice, however, the ADC may still provide a reading of 0. If a digital output of 1 is obtained from an analog input of 550 V, then:Offset error = Actual transition Ideal transition EO = 550 V 402.8 V = 141.2 VEO = 141.2 V / 805.6 V = 0.17

32、LSBWhen an analog input voltage greater than 0.5 LSB generates the first transition, the offset error is positive (refer to Figure 7 for an example of positive offset error).10/49DocID15067 Rev 3AN2834ADC errorsFigure 7. Positive offset error representation1. The error offset, EO, is shown in magent

33、a.When an analog input voltage of less than 0.5 LSB generates the first transition, the offset error is negative (refer to Figure 8 for an example of negative offset error).If the analog input voltage (VAIN) is equal to VSSA and the ADC generates a non-zero digital output, the offset error is negati

34、ve. This means that a negative voltage generates the first transition.Figure 8. Negative offset error representation1. The error offset, EO, is shown in magenta.DocID15067 Rev 311/49LJLWDO RXWSXW,GHDO WUDQVIHU FXUYH(2 !$FWXDO WUDQVIHU FXUYH9$,1/6%DL ELJLWDO RXWSXW,GHDO WUDQVIHU FXUYH(2 !$FWXDO WUDQV

35、IHU FXUYH9$,1/6%DL EADC errorsAN28342.1.2Gain errorThe gain error is the deviation between the last actual transition and the last ideal transition. It is denoted by EG.The last actual transition is the transition from 0xFFE to 0xFFF. Ideally, there should be a transition from 0xFFE to 0xFFF when th

36、e analog input is equal to VREF+ 0.5 LSB. So for VREF+= 3.3 V, the last ideal transition should occur at 3.299597 V.If the ADC provides the 0xFFF reading for VAIN VREF+ 0.5 LSB, then a negative gain error is obtained.ExampleThe gain error is obtained by the formula below: EG = Last actual transition

37、 ideal transitionIf VREF+ = 3.3 V and VAIN = 3.298435 V generate a transition from 0xFFE to 0xFFF then: EG = 3.298435 V 3.299597 VEG = 1162 VEG = (1162 V / 805.6 V) LSB = 1.44 LSBIf a full scale reading (0xFFF) is not obtained for VAIN equal to VREF+, the gain error is positive. This means that a vo

38、ltage greater than VREF+ will cause the last transition. Figure 9 shows a positive gain error while Figure 10 shows a a negative gain error.Figure 9. Positive gain error representation1. The gain error, EG, is shown in magenta.12/49DocID15067 Rev 3LJLWDO RXWSXW(* !,GHDO WUDQVIHU FXUYH$FWXDO WUDQVIHU

39、 FXUYH9$,1/6%DL EAN2834ADC errorsFigure 10. Negative gain error representation1. The gain error, EG, is shown in magenta.2.1.3Differential linearity errorThe differential linearity error (DLE) is the maximum deviation between the actual and ideal steps. Here ideal does not refer to the ideal transfe

40、r curve but to the ADC resolution. The DLE is denoted by ED. It is represented in Figure 11.ED = Actual step width 1 LSBIdeally, an analog input voltage change of 1 LSB should cause a change in the digital code. If an analog input voltage greater than 1 LSB is required for a change in digital code,

41、a differential linearity error is observed. The DLE therefore corresponds to the maximum additional voltage that is required to change from one digital code to the next.The DLE is also known as the differential non-linearity (DNL) error.ExampleA given digital output should correspond to an analog in

42、put range. Ideally, the step width should be 1 LSB. Let us assume that the digital output is the same over an analog input voltage range of 1.9998 V to 2.0014 V, the step width will be:2.0014 V 1.9998 V = 1.6 mV.ED is thus the voltage difference between the higher (2.0014 V) and the lower (1.9998 V)

43、 analog voltages minus the voltage corresponding to 1 LSB.DocID15067 Rev 313/49LJLWDO RXWSXW(*,GHDO WUDQVIHU FXUYH$FWXDO WUDQVIHU FXUYH9$,1/6%DL EADC errorsAN2834Figure 11. Differential linearity error representation1. The differential linearity error, ED, is shown in magenta.If VREF+ = 3.3 V, an an

44、alog input of 1.9998 V (0x9B1) can provide results varying between 0x9B0 and 0x9B2. Similarly, for an input of 2.0014 V (0x9B3), the results may vary between 0x9B2 and 0x9B4.As a result, the total voltage variation corresponding to the 0x9B2 step is: 0x9B3 0x9B1, that is, 2.0014 V 1.9998 V = 1.6 mV

45、(1660 V)ED = 1660 V 805.6 V ED = 854.4 VED = (854.4 V/805.6 V) LSB ED = 1.06 LSBLet us assume that no voltage greater than 2.0014 V will result in the 0x9B2 digital code when the step width is less than 1 LSB, ED is negative.2.1.4Integral linearity errorThe integral linearity error is the maximum de

46、viation between any actual transition and the endpoint correlation line. The ILE is denoted by EL. It is represented in Figure 12.The endpoint correlation line can be defined as the line on the A/D transfer curve that connects the first actual transition with the last actual transition. EL is the de

47、viation from this line for each transition. The endpoint correlation line thus corresponds to the actual transfer curve and has no relation to the ideal transfer curve.The ILE is also known as the integral non linearity error (INL). The ILE is the integral of the DLE over the whole range.14/49DocID1

48、5067 Rev 3$FWXDO LJLWDO RXWSXW 6WHS /6%ZLGWK( !/6%$FWXDO VWHS ZLGWK(,GHDO WUDQVIHU FXUYH$FWXDO WUDQVIHU FXUYH9$,1DL EAN2834ADC errorsFigure 12. Integral linearity error representation1. The integral linearity error, EL, is shown in magenta.ExampleIf the first transition from 0 to 1 occurs at 550 V a

49、nd the last transition (0xFFE to 0xFFF) occurs at 3.298435 V (gain error), then the line on the transfer curve that connects the actual digital codes 0x1 and 0xFFF is the endpoint correlation line.DocID15067 Rev 315/49LJLWDO RXWSXWH9$,1w99DL EVIHU FXUY(/$FWXDO WUDQADC errorsAN28342.1.5Total unadjust

50、ed errorThe total unadjusted error (TUE) is the maximum deviation between the actual and the ideal transfer curves. This parameter specifies the total errors that may occur, thus causing the maximum deviation between the ideal digital output and the actual digital output. TUE is the maximum deviatio

51、n recorded between the ideal expected value and the actual value obtained from the ADC for any input voltage.The TUE is denoted by ET. It is represented in Figure 13.The TUE is not the sum of EO, EG, EL, ED. The offset error affects the digital result at lower voltages whereas the gain error affects the digital output for higher voltages.ExampleIf VREF+ = 3.3 V and VAIN = 2 V, the ideal result is 0x9B2. However, if the conversion result of 0x9B4 is obtain