数字电子技术,英文版,chapter07.ppt

1、7INTRODUCTION TOPROGRAMMABLE LOGIC DEVICES可编程逻辑器件,7-1 PLD ARRAYS AND CLASSIFICATIONSPLD阵列和分类,Whats PLD?,PLD is abbreviated from “programmable logic device”. A PLD consists of a large array of AND gates and OR gates that can be programmed to achieve specified logic functions. PLDs, particularly PAL a

2、nd GAL devices, can be used to replace SSI and MSI logic devices in most types of applications, resulting in fewer parts and lower cost.,Programmable Arrays,All PLDs consist of programmable arrays. A programmable array is essentially a grid of conducts that form rows and columns with a fusible link

3、at each cross point.,The OR Array（或阵列）,This type of array consists of an array of OR gates connected to a programmable matrix with fusible links at each cross point of a row and column. The array is programmed by blowing fuses to eliminate selected variables from the output functions.,The AND Array（

4、与阵列）,This type of array consists of an array of AND gates connected to a programmable matrix with fusible links at each cross point. The array is programmed by blowing fuses to eliminate selected variables from the output functions.,Classification of PLDs,Programmable Read-Only memory (PROM) 可编程只读存储

5、器 Programmable Logic Array (PLA), aka, FPLA 可编程逻辑阵列 Programmable Array Logic (PAL) 可编程阵列逻辑 Generic Array Logic (GAL) 通用阵列逻辑,PROM,The PROM consists of a set of fixed (nonprogrammable) AND gates as a decoder and a programmable OR array. The PROM is used primarily as an addressable memory and not a log

6、ic device because of limitations imposed by the fixed AND gates.,PLA,The PLA consists of a programmable AND array and a programmable OR array.,PAL,The PAL consists of a programmable AND array and a fixed OR array with output logic. The PAL is the most common one-time PLD and is implemented with bipo

7、lar technology (TTL or ECL).,GAL,The GAL consists of a programmable AND array and a fixed OR array with programmable output logic. The main differences between GAL and PAL are (a) the GAL is reprogrammable because it uses E2CMOS technology and (b) the GAL has programmable output configurations.,7-2

8、PROGRAMMBLE ARRAY LOGIC (PAL),Basic Structure,The PAL consists of a programmable array of AND gates and a fixed array of OR gates. This structure allows any sum-of-products (SOP) logic expression with a defined number of variables to be implemented. Each programmable array is essentially a grid of c

9、onductors forming rows and columns with a fuse cell at each cross point.,Implementing a Sum-of-Products Expression,When the connection between a row and column is required, the fuse is left intact. When no connection between a row and column is required, the fuse is blown open during the programming

10、 process.,Simplified Symbols,Since PALs are very complex integrated circuit devices, manufacturers have adopted a simplified notation for the logic diagrams to keep them from being overwhelmingly complicated.,Example 7-1,Show how a PAL is programmed for the following 3-variable logic function:,Block

11、 Diagram,The AND array outputs go to the OR array, and the output of each OR gate goes to its associated output logic.,Output Combinational Logic,The following are types of PAL output logic: Combinational output Combinational input/output Programmable polarity output,Standard PAL Numbering,Standard

12、PALs come in a variety of configurations, each of which is identified by a unique part number.,PAL 10 L 8 Prefix The number of inputs, including outputs that can be configured as inputs The type of output: L/H/P The number of outputs Suffixes that specify speed, package type, and temperature range,B

13、lock Diagram of the PAL16L8,10 dedicated inputs, 2 dedicated outputs, 6 pins that can be used either as inputs or as outputs.,7-3 GENERIC ARRAY LOGIC (GAL),Basic Structure,The GAL consists of a reprogrammable array of AND gates and a fixed array of OR gates. This structure allows any sum-of-products

14、 (SOP) logic expression with a defined number of variables to be implemented.,Basic Structure,Each reprogrammable array is essentially a grid of conductors forming rows and columns with an E2CMOS cell at each cross point.,Implementing a Sum-of-Products Expression,When the connection between a row an

15、d column is required, the cell is programmed to be on. When no connection between a row and column is required, the cell is programmed to be off.,Example 7-3,The programmed array using simplified notation is shown below.,Block Diagram,The AND array outputs go to the output logic macrocells (OLMC).,S

16、tandard GAL Numbering,Standard GALs come in a variety of configurations, each of which is identified by a unique part number.,GAL 16 V 8 Prefix The number of inputs, including outputs that can be configured as inputs Variable-output configuration The number of outputs Suffixes that specify speed, pa

17、ckage type, and temperature range,7-4 THE GAL22V10,Block Diagram of the GAL22V10,GAL22V10 Package Diagrams,The Output Logic Macrocells (OLMCs),Logic diagram,The Output Logic Macrocells (OLMCs),Four configurations (S1S0) Combinational mode with active-LOW output (10) Combinational mode with active-HI

18、GH output (11) Registered mode with active-LOW output (00) Registered mode with active-LOW output (01),The Output Logic Macrocells (OLMCs),Combinational mode with active-LOW output (S1S0=10),The Output Logic Macrocells (OLMCs),Combinational mode with active-HIGH output (S1S0=11),The Output Logic Macrocells (OLMCs),Example 7-5 Determine th