05-DC-命令行-层次划分

2024/11/91逻辑综合工具DCPart2层次划分与编码风格集成电路EDA技术实验2024/11/92CONTENTS

Synopsys工艺库层次划分与编码风格设计约束与脚本编写设计优化2024/11/93层次划分与编码风格Whatdowegainby“partitioningforsynthesis”?

Betterresults--smallerandfasterdesigns

Easiersynthesisprocess--simplifiedconstraintsandscripts

Fastercompiles--quickerturnaround

codereuse合理的设计划分和良好的编码风格是成功综合的关键。2024/11/94层次划分与编码风格设计划分的方法分为HDL划分和DC中的划分HDL划分是根据原则通过HDL编码对设计进行划分；DC中的划分是在DC通过专门的命令来改变HDL中的划分和层次结构。HDL划分的原则将相关的组合逻辑划分到一起消除胶连逻辑（gluelogic）模块的输出应使用FF或划分以FF为边界合理限制模块的大小分离用于同步多个时钟的模块划分顶层（corelogic,pads,clocks,andJTAG）DC划分命令：group、ungroup2024/11/95EliminateUnnecessaryHierarchy2024/11/96PartitionatRegisterBoundaries2024/11/97AvoidGlueLogic:Example2024/11/98BalanceBlockSizeWithRunTimes2024/11/99PartitioningwithinDesignCompilerThegroupandungroupcommandsmodifythepartitionsinadesign2024/11/910HDL语言：

是“硬件描述语言”，即HardwareDescriptionLanguage,而不是“硬件设计语言”，HardwareDesignLanguage.

因此电路设计必须遵循RTL的模式来编写代码，而不能随心所欲地只写出符合语法的代码。

逻辑综合是模板驱动的，如果代码用综合工具理解和期望的模板写出，那么结果正确且可预知。inference&instance逻辑推断2024/11/911锁存器推断当条件语句没有完全指定时推断出锁存器；一个非完全指定的case语句也推断出锁存器。2024/11/912寄存器推断当在always块的敏感信号表中指定了一个边沿，则推断出寄存器。带复位带置位2024/11/913多路选择器推断使用case语句的多路选择器if和case使用if：优先级编码器使用case：避免锁存器(default)full_caseparallel_caseifstatementsTheifandif-elsestatementsmaybethemostcommonbranchingstatementsYoucannestif-elsestatementsintwowaysif(sel==3)y=d;elseif(sel==2)y=c;elseif(sel==1)y=b;elseif(sel==0)y=a;if(sel[1])if(sel[0])y=d;elsey=c;elseif(sel[0])y=b;elsey=a;Innestedifsequences,everyelseisassociatedwiththeclosestpreviousifatthesamenestinglevel.NoteveryifwillnecessarilybeassociatedwithanelseIfstatementsThefirstvalidtestexecutesthatbranchConditionscanoverlapTheconditionsofanif-else-ifstatementsaretestedinorder–the1stconditionhavingthehighestpriority,the2ndhavingthenexthighestpriority,etc.moduleif_example(input[3:0]a,input[3:0]b,input[3:0]c,input[3:0]d,outputreg[3:0]y);

always@(aorborcord)if(d==4'b0000)y=a;elseif(d<=0101)y=b;elsey=c;endmoduleWhatwouldbetheeffectofswappingtheifand

elseifconditions??Ifsynthesizestomuxstructured<=0101d=0000abcy1010ifstatementsCodethefollowingconditionallogicmoduleif_example(inputa,inputb,inputc,inputctrl,input[3:0]f,outputregd);

always@(aorborcorctrloff)if(f<4’b0110)d=a&b;elseif(ctrl)d=1’b0;elsed=c;endmodulef<4’b01101’b0cd1010abctrlcasestatementsThecasestatementislikeanif-elsestatementthatusesidentityoperators.Thecasestatementmaysometimesbemorereadable.if(sel==3)y=d;elseif(sel==2)y=c;elseif(sel==1)y=b;elseif(sel==0)y=a;case(sel)3:y=d;2:y=c;1:y=b;default:y=a;endcaseNote:TheVerilogcasestatementautomaticallybreaksafterthefirstmatch.casestatementsNotethatexpressionischeckedagainstthecaseitemsintheordertheyappear.Itisnotillegaltohavethesamevalueappearmorethanonceinthelist.Becausethelistischeckedinorder,thesecondvaluewillalwaysbemaskedbythefirst.modulecase_ex(a,b,c,d,y);input[3:0]a,b,c,d;outputreg[3:0]y;always@(aorborcord)case(d)0:y=a;1,2,3,4,5:y=b;//1st5:thisbranchtakenwhend=55,6:y=c;//2nd5:thisbranchmaskedwhend=5default:y=4'b0000;endcaseendmodule2024/11/919CompilerDirectivefull_casealways@(active[3]oractive[2]oractive[1]oractive[0])begincase({active[3],active[2],active[1],active[0]})//synopsysfull_case4’b1000:temp=3’b010;4’b0100:temp=3’b011;4’b0010:temp=3’b100;4’b0001:temp=3’b101;4’b0000:temp=3’b000;endcaseendalwaysvec[15:4]=12’h000;alwaysvec[0]=0;always@(posedgeclk)vec[3:1]=temp;2024/11/920CompilerDirectiveparallel_casealways@(active[3]oractive[2]oractive[1]oractive[0])begintemp=3’b000;case(1’b1)//synopsysparallel_caseactive[3]:temp=3’b010;active[2]:temp=3’b011;active[1]:temp=3’b100;active[0]:temp=3’b101;endcaseendalwaysvec[15:4]=12’h000;alwaysvec[0]=0;always@(posedgeclk)vec[3:1]=temp;2024/11/921SynthesisofloopStatementsInsynthesis,forloopsare“unrolled”duringtra