数电英文版全册配套课件

《数电(英文版）》全册配套课件2DigitalLogicDesignandApplication

ChenYan

Lecture#1IntroductionUESTC,Spring20113InstructorChenYanOffice:研究院大楼508

航空航天学院SchoolofAstronautics&AeronauticsEMAIL:blastchen@4ResourcesTextbook:DIGITALDESIGN–Principles&Practices,(FourthEdition),JohnF.Wakerly,HigherEducationPress,2007

References:数字逻辑设计及应用，姜书艳主编，清华大学出版社，2007数字电子技术基础（第5版），阎石主编，高等教育出版社，2007数字设计——原理与实践（第4版），JohnF.Wakerly,林生等译,机械工业出版社，20075ResourcesCourseWebpage95/wlxt/index.aspx电子科技大学/互动教学空间/网络学堂/自动化工程学院/数字逻辑设计及应用[姜书艳]/教学录像

部分习题解答/programs.univXilinx的大学计划，提供了大量的产品资料、课程资料以及用于数字设计实验课程的芯片和插件Prerequisites《电路分析基础》《模拟电路基础》AboutthenameOthernamesAssociationbetweenDigital&LogicalJin.UESTC.6Whatdoesdigitaltech.do?7电视技术雷达技术通信技术计算机、自动控制航空航天数码相机MP3、MP4人类社会进入信息数字化的时代，“数字逻辑”是数字技术的基础，是电子信息类各专业的主要技术基础课程之一。“digitalize”：许多传统使用模拟技术的领域转而使用数字技术。8TopicstobeCoveredIntroduction,NumberSystemsandCodes: 1½weeksLogicsignalsandGates,CMOSLogic:1½weeksCombinationalLogicDesignPrinciples:2-3weeksSwitchingAlgebra,Combinational-CircuitAnalysisandSynthesisCombinationalLogicDesignPractices:3weeksDecoders,Encoders,Multiplexers,Comparators,etc.

HardwareDescriptionLanguages:1weekSequentialLogicDesignPrinciples:2-3weeksLatches,Flip-Flops,ClockedSynchronousState-MachineAnalysisandDesignSequentialLogicDesignPractices: 3weeksSSILatchesandFlip-Flops,Counters,ShiftRegisters,Iterative,…Other:Memory,CPLDSandFPGAS,A/D,D/ACircuits:1weeks一、concepts&fundamentals二、集成电路为主；逻辑功能为主三、重视实践本课程的重点是数字电路的基本概念、基本原理、分析方法、设计方法和实验调试方法。只要掌握了基本的原理和方法，我们就可以分析给出的任何一种数字电路；也可以根据提出的任何一种逻辑功能，设计出相应的逻辑电路。对于各类数字集成电路器件，重点是掌握他们的外部特性，包括逻辑功能和输入、输出端的电气特性。为了更好的理解和运用电路器件的外部特性，需要理解他们的输入电路和输出电路的结构及其原理。至于内部的电路结构和详细工作过程都不是重点，不需要去记忆。通过实验的训练，加深对理论知识的理解和掌握，同时更重要的是要学习和掌握电子技术实验的研究方法。将理论和实际有机地结合，学会用实验的方法分析和解决实际问题。Conceptsofteaching&learning10GradesHomeworksandQuizzesinclass—15%ProjectsandPaper—15%MidtermExam—30%FinalExam—40%11Chapter1IntroductionWelcometotheworldofdigitaldesign.DigitalLogicDesignandApplication12Chapter1Introduction1.1AboutDigitalDesignAboutPrinciplesandPracticesImportantThemesinDigitalDesign…(P2)*131.2Analogvs.DigitalAnalog:1.2Analogvs.DigitalJin.UESTC.14Primaryparameters:frequency,bandwidth、powerBasicdevice：transistorsworkingatamplifyarea.Analog:valuesvaryoverabroadrangecontinuouslytvrectangularwave1forHigh；0forLow010011010特点：数值的大小和每次的增减都是量化单位的整数倍。Presentedasbinarycodesystem1.2Analogvs.Digital1.2Analogvs.DigitalTheproblemforanalogsignal…Theadvantagesofdigitalsignal…16signaldegradationamplification

模拟信号在传输过程中失真数字信号仍然可以保持

0、1抗干扰性强;便于存储;便于分析和设计；便于利用计算机、DSP等进行信号处理.电路中的电子器件工作在开关状态，易于实现，便于集成化缺点：其表现形式的多样化决定了对其的处理也是复杂多样的。171.2Analogvs.DigitalDigitalsystemAnyinputsandoutputscanonlybe1or0!181.3DigitalDevicesGates（门）—themostbasicdigitaldevicesFlip-Flops（触发器）—adevicethatstoreseithera0or1CombinationalCircuits（组合电路）SequentialCircuits（时序电路）ANDgateORgateNOTgateorinverter191.4ElectronicAspectsofDigitalDesign

（数字设计的电子技术）Howtorealizelogic0and1inarealcircuit?逻辑上的0和1在物理上如何实现？Whatistherangeofanalogvaluewitheachlogicvalue?什么电平范围对应逻辑0或1？Howtoproduceandfigureoutthesignalinaproperrange?如何正确产生和识别处于适当范围的信号？TheassociationbetweenDigitalandAnalog数字与模拟之间的关系201.5SoftwareAspectsofDigitalDesign*Whatdoessoftwarecando?Softwaretoolshelptoimprovethedesigner’sproductivity,thecorrectnessandqualitydesigns.软件工具有助于提高设计的效率、正确性和质量。SeveralSoftwareTools几种软件工具P9Pspise,multisim,电路仿真MaxPlus,QuatusII,VHDL仿真protel,powerPCB，制版软件1.6IntegratedCircuits21Relay继电器AdvancesofDigitalElectronictechnologies221.6IntegratedCircuitsAdvancesofDigitalElectronictechnologies数字电子技术的进展20世纪40年代，宾夕法尼亚大学，第一部电子数字计算机（Eniac），采用真空管（VacuumTube）使用了17468个真空管占地457平米重30吨耗电160KW每秒可以完成5000次+，或385次*，或40次/，或3次开方运算231.6IntegratedCircuits(集成电路IC)20世纪50年代（1947年），双极型晶体管（BJT）出现；60年代，TTL逻辑出现，集成电路出现TTL:Transistor-TransistorLogic80年代开始，MOS电路开始逐步取代TTL电路，现在CMOS占领了世界IC市场的绝大部分CMOS:ComplementaryMOS241.6IntegratedCircuits单个硅片上的一个或多个门电路的集合体，就叫做集成电路。wafer(单晶硅片)

die(模片)packagingDualIn-line-pinPackage(DIP)双列直插式封装（P13）0.254mm15mm251.6IntegratedCircuits261.6IntegratedCircuitsSmall-ScaleIntegration(SSI，小规模集成):门1-20GatesMedium-ScaleIntegration(MSI，中规模集成):功能构件20-200GatesLarge-ScaleIntegration(LSI，大规模集成):一个系统200-200,000GatesVeryLarge-ScaleIntegration(VLSI，超大规模集成):包含FPGA的系统Over1,000,000TransistorsSystemOnChip(SOC)片上系统集成系统TinyScaleIntegration(TSI)微小规模集成1.6IntegratedCircuitsJin.UESTC.27Question：Whatifthereissomethingwrongwiththealready-madeIC?Howtodebuggingit？Thesolutionis……ProgrammableLogicDevices（PLD）281.7ProgrammableLogicDevicesProgrammableLogicDevice(PLD,可编程逻辑器件)AND-ORcircuit1.7ProgrammableLogicDevicesProgrammableLogicArray(PLA,可编程逻辑阵列)ProgrammableArrayLogic(PAL,可编程阵列逻辑)ComplexPLD(CPLD,复杂可编程逻辑器件)Field-ProgrammableGateArray(FPGA,现场可编程门阵列）29301.8Application-SpecificICs

专用集成电路（ASIC）Semi-CustomIC(半定制IC)Non-RecurringEngineering(NRE)Cost(非再现工程成本）:$30,000-$50,000CustomIC(全定制IC）NRECost:Over$250,000Ifyouputthedesignintroducedinthistextbookintoapracticalchipmanufactory,you’rerequiringaASICproducing.311.9Printed-CircuitBoardsPrinted-WiringBoards(PWB,印制线路板)多层，1/16”钻孔连线：10-50mil@3mil焊接1.9Printed-CircuitBoardsSurface-MountTechnology(SMT,表面安装技术)321.9Printed-CircuitBoardsMulti-ChipModule(MCM,多芯片模块）Jin.UESTC.33MCM在多层印制板(PCB)和表面安装技术(SMT)的基础上发展起来的新一代微电子封装与组装技术，是实现系统集成的有力手段。信号传输速度、电性能以及可靠性等方面独具优势，是目前能最大限度地提高集成度、提高高速单片IC性能，制作高速电子系统，实现整机小型化、多功能化、高可靠性、高性能的最有效途径。341.10DigitalDesignLevelsDevicePhysicsandICManufacturingProcessesLevel（物理级：器件物理和IC制造过程）TransistorLevel（晶体管级）GatesStructureLevel（门电路结构级）LogicDesignLevel（逻辑设计级）OverallSystemDesign（整体系统设计）本课程

*35Example:amultiplexerwith2datainputbitsABSZABSZ6transistors14transistorsHomework1.6以“数字电路设计的层次”为主题，标题自拟，完成一篇2000~3000字左右的小论文。手写、打印均可，下周四提交。3637DigitalLogicDesignandApplication

ChenYan

Lecture#2UESTC,Spring2011Chapter3DigitalCircuitsGiveaknowledgeoftheElectricalaspectsofDigitalCircuits

学习要求38掌握：CMOS逻辑电平和噪声容限；CMOS逻辑基本门的电路结构;理解：CMOS逻辑电路的稳态和动态电气特性；理解：特殊的输入输出电路结构;了解：利用仿真软件对CMOS基本逻辑门的静态特性和动态特性进行仿真。了解：作为电子开关运用的二极管、双极型晶体管、MOS场效应管的工作方式；了解：其他类型的逻辑电路：TTL,ECL等；了解：不同类型、不同工作电压的逻辑电路的输入输出逻辑电平规范值以及它们之间的连接配合的问题。电路成本、速度与基本电路规模的关系。3.1LogicSignalsandGatesDigitlogichidethepitfallsoftheanalogworldbymappingtheinfinitesetofrealvaluesforaphysicalquantityintotwosubsetscorrespondingtojusttwopossiblenumbersorlogic：0an139InfiniteSignaloftherealworldTwovaluesintheDigitalLogicworldlogical

abstraction3.1LogicSignalsandGates40Tab.3-1themapingofpracticalphysicalsignaltothelogicalsignal玩过碟仙、笔仙的游戏吗？3.1LogicSignalsandGates41Bufferamplifier1theminmialinputhighvoltagelevelvoltagelevelWeakstrong3.1LogicSignalsandGates423.1LogicSignalsandGatesMethodsofdescription,analysisanddesigntheabstractlogiccircuitsswitchingalgebraTruthtable/StateTable43X+X=XX*X=X……44AxiomsofLogicAlgebraX=0,ifX1(若X

1,则X=0)X=1,ifX0(若X

0,则X=1)

0’=1

1’=00·0=0 1+1=11·1=1 0+0=00·1=1·0=0 1+0=0+1=145BasicLogicFunction—AND000010100111ABZLogicEquationZ=A·BSwitch:1-on,0-offLamp:1-light,0-unlightedAnANDgateproducesa1outputifandonlyifallitsinputsare1.TruthTable&ABZABZLogicSymbolABZ46BasicLogicFunction:ORLogicEquation

:

Z=A+BABZTruthTableABZAnORgateproducesa1outputifandonlyifoneormoreinputsis1.000011101111≥1ABZABZLogicSymbol

47AZ0110TruthTableLogicEquationZ=A=A’AZRToproduceanoutputvaluethatistheoppositeofitsinputvalue.CommonlycalledanInverter.1ZAAZLogicSymbolBasicLogicFunction:NOT48TruthTable&≥1493.1LogicSignalsandGatesThephysicalaspectsofdigitalcircuitsPhysicalrealizationWorkingprinciplesElectricalcharactersChap.3503.1LogicSignalsandGatesHowtogettheHIGHandLOWVoltage?positivelogic10negativelogic10HighLowConsultFig.3-62forlogicalvoltagecomparetionVOUTVINVccR获得高、低电平的基本原理513.2LogicFamiliesAlogicfamilyisacollectionofdifferentICchipsthathavesimilarinput,output,andinternalcircuitcharacteristics,butthatperformdifferentlogicfunctions.Chipsofsamefamilycanbeconnectedtoperformarbitarylogicfunction.(Fig.6-62)Chipsfromdifferentfamiliesmaynotbecompatible.TTLfamilies(Tab.3-10)CMOSlogic(Fig.3-62)52SomeTermsSemiconductordiode,半导体二极管Bipolarjunctiontransistor,双极结型晶体管Integratedcircuit,集成电路Bipolarlogicfamily,双极型逻辑系列Transistor-transistorlogic,TTL,晶体管-晶体管逻辑Metal-oxidesemiconductorfield-effecttransistor,MOSFET,金属氧化物半导体场效应晶体管ComplementaryMOS,CMOS,互补MOS533.3CMOSLogic1.CMOS

LogicLevelsLogic1(HIGH)

Logic0(LOW)5.0V3.5V1.5V0.0V

undefinedlogiclevel

ACMOSLogicCircuitusesnotonly5-Voltpower-supplyvoltage,butotherpower-supplyvoltages,suchas3.3,2.7volts.542.MOSTransistorsTwoTypes:N-ChannelandP-ChannelAninputvoltagecontrolstheresistancebetweendrainandsource.552.MOSTransistorsNormally,Vgs>=0IfVgs=0Rds

isveryhigh(>106Ω)

Thetransistoris“Off”.

increaseVgs

decreaseRds

whenRds

isverylow(<=10Ω)

thetransistoris“On”.Aninputvoltagecontrolstheresistancebetweendrainandsource.562.MOSTransistorsTwoTypes:P-ChannelNormally,

Vgs<=0If

Vgs=0Rds

isveryhigh.

Thetransistoris“Off”.Vgs

Rds

when

Rds

isverylow,

thetransistoris“On”.Aninputvoltagecontrolstheresistancebetweendrainandsource.注意，空穴的概念，以及空穴导电的实质还是电子导电。2.MOSTransistorsTwoTypesMOS:N-ChannelandP-ChannelAninputvoltagecontrolstheresistancebetweendrainandsourceRgs、RgdisextremelyhighWhatevervoltageonGate，igs,igd

≈0(1µA）iscalledLeakagecurrent.TherearecapacitivecouplingbetweentheGate&Source,Gate&Drain5758BasicMOSon-offCircuitvI+–vO–+iD+VDDRDDGSQ1:CanwereplaceNMOSwithPMOS?Q2:HowtochoosetheloadresistanceRD?IfinputisL,transistoris“off”andoutputisH.

IfinputisH,transistoris“on”,outputisL.

593.BasicCMOSInverterCircuit1.VIN=0.0V(L)VGS1=0.0V，Q1

offVGS2=VIN–VDD=–5.0V,Q2onVOUT

VDD=5.0V(H)2.VIN=5.0V(H)VGS1=5.0V，Q1onVGS2=VIN–VDD=0.0V,Q2offVOUT

0.0V(L)VDD=+5.0VVOUTVINQ2p-channelQ1n-channelGDS2S160VDD=+5.0VVOUTVINQ2p-channelQ1n-channelSwitchmodel61CMOSinverterlogicaloperationVCCVinVoutONwheninputislow

ONwheninputishighVDD=+5.0VVOUTVINQ2p-channelQ1n-channel一个输入同时控制两个MOS管624.CMOSNANDGateUse2ntransistorsforn-inputgate1.Ifbothinputsarehigh,BothQ1andQ3are“on”,BothQ2andQ4are“off”,

Zislow(

0V).2.Ifeitherinputislow,eitherQ1orQ3is“off”,eitherQ2orQ4is“on”,Zishigh(

VDD).VDD=+5.0VZABQ1Q2Q4Q3634.CMOSNANDGateCMOSNANDmoreinputs(3)Can’tbeaddedunlimitedlyFanIn64Thenumberofinputsthatagatehaveiscalledfan-in.Theadditive“on”resistanceofseriestransistorslimitsthefan-inofCMOSgates.Gateswithalargenumberofinputscanbemadebycascading(级联)gateswithfewerinputs.654.CMOSNORGateLikeNAND―2ntransistorsforn-inputgate

1.Ifbothinputsarelow,bothQ1andQ3is“off”,bothQ2andQ4is“on”, Zishigh(

VDD).

2.Ifeitherinputishigh,eitherQ1orQ3is“on”,eitherQ2orQ4is“Off”,Zislow(0V).VDD=+5.0VZABQ1Q2Q4Q366NANDvs.NORForagivensiliconarea,PMOStransistorsare“weaker”thanNMOStransistors.Result:NANDgatesarepreferredinCMOS.675.CMOSAOIGatesZ=(A·B+C·D)’AND-OR-INVERT从NMOS的连接与逻辑“与”、“或”的关系来构造；非是“免费”获得的VDD=+5.0VABZCD685.CMOSAOIGatesZ=(A·B+C·D)’696.Non-invertingGatesnoninvertingbuffer2-inputANDgateVDD=+5.0VAZIttypicallyisnotpossibletodesignanon-invertinggatewithasmallernumberoftransistorsthananinvertingone.Circuitdiagram:P94Figure3-197.BuildinganarbitarycircuitwithCMOS70每个CMOS门电路都由NMOS和PMOS两部分组成，并且每个输入都同时控制两个管子；NMOS管串联可实现与非操作，并联可实现或非操作；PMOS管正好相反；NMOS管串联时PMOS一定并联；NMOS管并联时PMOS一定串联——对偶关系。PMOS网络和NMOS网络不能同时导通非是“免费”获得的课堂练习

CMOSOAIGates71F=((A+B)·(C+D))’Fig.3-22课堂练习72Z=(A’+B·C)’课堂练习73Z=A+B=A’·B+A·B’XORABZ000011101110A’ZBAB’A’ABB’课堂练习74(AOIGates)’Z=A’·B+A·B’=(A’·B+A·B’)’’=((A’·B+A·B’)’)’XORZ=(A·B+C·D)’753.7OtherCMOSInputandOutputStructures1.TransmissionGatesGates-CMOSTransmissionGatesWhenEN=0,EN_L=1,thetransistorsare“off”,AandBaredisconnected.WhenEN=1,EN_L=0,thetransistorsare“on”,

AandBareconnectedwithalow-impedance.

ENEN_LABBidirectionaldevice双向器件门的导通时延大于传输时延3.7OtherCMOSInputandOutputStructures761.TransmissionGates-NMOS773.7OtherCMOSInputandOutputStructures1.TransmissionGates-PMOS0.1V0V0V0.1V0.1V0.1V0V0.2V0.1V0.2V3.7OtherCMOSInputandOutputStructuresApplicationofTransmissionGates78s’Fig.3-46ZSVCCXYMUX(Multiplexer)s’s’X

YssZ=S’·X+S·Y

010011S=0;T1on,T2off;Z=XS=1;T1off,T2On;Z=Y

ZYXST1T2792.

Three-StateOutputsVCCZENAIfEN=0,C=1,Tp=“off”B=1,D=0,Tn=“off”

Z=Hi-impedancestateor

floatingstateIfEN=1C=A’,B=0,D=A’

Z=A(0or1)BCDTpTnAENOUTLogicSymbol还有很多其他三态缓冲器件类型，其应用主要是三态总线803.

Open-DrainOutputsABZVCCVCC’Rpull-upresistanceABZLogicSymbolAssmallaspossible,tominimizetherisetime.Cannotbearbitrarilysmall,itisdeterminedbyIOLmaxpassivepull-up无源上拉Applications:drivingmultisourcebuses;drivingLEDs;performingwiredlogic.

3.

Open-DrainOutputs81Pull-upresistorvalue上拉电阻阻值的范围ABZVCCRRMin=VCC-VOLMax

iRiR=IOLMax-iLRmax=VCC-VOHMiniRiR=iLeak+iLVout=Rn

Rn+RVCCLH3.

Open-DrainOutputs

DrivingLEDsLED点亮的条件是：使Vz为低电压，与Vcc有1.6V的电压差，并且保证ILED≥10mA82VOLmaxVCC=VLED+VOL+VR=VLED+VOL+R*ILEDR

=VCC-VLED-VOLMaxILEDmin833.

Open-DrainOutputs

Multi-sourceBuses84ABZVCCVCCRCDVCCZ=Z1·Z2=(A·B)’·(C·D)’=(A·B+C·D)’WiredLogicofOpen-DrainOutputsZ1Z2WiredAND(线与)第4章反演定理852.输出电平？？造成逻辑混乱1.很大的负载电流同时流过输出级可使门电路损坏3.

Open-DrainOutputsVCCAZactivepull-up有源上拉VCCB低高有源上拉的CMOS器件其输出端不能直接相联100

>1M

100

>1M

Fighting冲突864.Schmitt-TriggerInputsVOUTVIN5.02.12.95.0I-OtransfercharacteristicVT+VT-inputswitching

thresholdVT+VT-Usefeedbackinternallyshifttheswitchingthreshold.采用内部反馈，边沿更陡Hysteresis(滞后):thedifferencebetweenthetwothresholds.LogicSymbol:87ApplicationsofSchmitt-Trigger波形变换VT88ApplicationsofSchmitt-Trigger脉冲整形89ApplicationsofSchmitt-Trigger脉冲鉴幅Backups9091DigitalLogicDesignandApplication

ChenYan

Lecture#3CMOSElectricalBehaviorUESTC,Spring201192LastLecturePositiveLogicandNegativeLogicCMOSLogic93LastLectureNAND,NOR,AOI,OAI2ntransistorsforn-inputgateNotice:theadditive“on”resistanceoftransistorsPMOS网络NMOS网络OutI1InI1In……LastLectureTransmissionGatesTri-StategatesDrainopengatesSchmitt-triggerinput94953.4ElectricalBehaviorofCMOSCircuitsDigitalanalysisworksonlyifcircuitsareoperatedinspec:PowersupplyvoltageTemperatureInput-signalqualityOutputloadingMustdosome“analog”analysistoprovethatcircuitsareoperatedinspec.Fan-inspecsFan-outspecsTiminganalysis(setupandholdtimes)963.4ElectricalBehaviorofCMOSCircuitsOverviewLogicVoltageLevelsDCNoiseMarginsFan-OutSpeedPowerConsumptionNoiseElectrostaticDischarge(静电放电)Open-DrainOutputsThreeStateOutputsnotlogical973.4ElectronicBehaviorofCMOSCircuitsANANDGateDataSheetsandSpecifications(P99Table3-3)983.5CMOSSteady-StateElectricalBehavior3.5.1LogicLevelsandNoiseMarginsVDD=+5.0VVOUTVINTpTn0101991003.5CMOSSteady-StateElectricalBehavior3.5.1LogicLevelsSpecificationsHIGHABNOMALLOWVOLmaxVOHminTheinputvoltagesaredeterminedmainlybyswitchingthresholdsofthetransistors,whiletheoutputvoltagesaredeterminedmainlybythe“on”resistanceofthetransistors.VILmaxVIHminVCC−0.1VGND+0.1V70%VCC30%VCCPower-supplyrails:VCCandGND1013.5.1DCNoiseMargin30%VCC−0.1VHIGHABNOMALLOWVOLmaxVILmaxVIHminVOHminHigh-stateDCnoisemarginLow-stateDCnoisemargin3.5CMOSSteady-StateElectricalBehavior3.5.2CircuitBehaviorwithResistiveLoadsResistiveLoadsdiscreteresistorTTLandothernon-CMOSloadCurrentconsumptiondevice102whichrequirenontrivialamountsofcurrenttooperateCMOSdevicehasveryhighinputimpedance,itbehavesasideallogicdevice.3.5.2CircuitBehaviorwithResistiveLoads103WhentheoutputofCMOScircuitisconnectedtoaresistiveload,theoutputbehaviorisnotasidealaswedescribedpreviously.Theonresistor(non-zero)willleadtoanon-zerovoltagedropwhichwillcausetheL-outputvoltagegreaterthanVOLMax

ortheH-outputvoltagelowerthanVOHMin.UseresistivemodeltoanalysistheCMOScircuitbehaviorwithresistiveloads.任何只包含电压源和电阻的双端网络，可由一个电压源和一个电阻串联组成的戴文宁等效电路进行模型化。所有独立源为零值时所得的网络求等效电阻时，电压源用短路代替1043.5.2CircuitBehaviorwithResistiveLoadsVCCAZresistivemodel105VCC=+5.0VRp>1M

RnResistiveLoadVOLmaxIOLmaxWhenoutputisLOW,VOUT<=VOLmaxthecurrentflowsfromthepowersupply,throughtheloadandthroughthedeviceoutputtoground.Thedeviceoutputissaidtosinkcurrent(灌电流).IOLmax:ThemaximumcurrenttheoutputcansinkintheLOWstatewhilestillmaintaininganoutputvoltagenogreaterthanVOLmax.106VCC=+5.0VRpRn>1M

ResistiveLoadVOHminIOHmaxWhenoutputisHIGH,VOUT>=VOHminthecurrentflowsfromthepowersupply,outofthedeviceoutputandthroughtheloadtoground.Thedeviceoutputissaidtosourcecurrent(拉电流).IOHmax:ThemaximumcurrenttheoutputcansourceintheHIGHstatewhilestillmaintaininganoutputvoltagenogreaterthanVOHmin.107Output-voltagedropResistanceof“off”transistoris>1Megohm,butresistanceof“on”transistorisnonzero,Voltagedropsacross“on”transistor,V=IRFor“CMOS”loads,currentandvoltagedroparenegligible.ForTTLinputs,LEDsterminations,orotherresistiveloads,currentandvoltagedroparesignificantandmustbecalculated.108VOUT=0VCC=+5.0VRThevVThev

+VIN=1WiththeoutputLOW,theestimatesinkcurrentisVCC=+5.0VRThevVThev

+VOUT=1VIN=0WiththeoutputHIGH,theestimatedsourcecurrentisIdealBehavior1093.5.3CircuitBehaviorwithNonidealInputsVCC=+5.0V400

2.5k

VIN1.5VVOUT4.31VVCC=+5.0V4k

200

VIN3.5VVOUT0.24VTheoutputvoltagedeterioratesfurtherwitharesistiveload.What’sworseis:Outputcurrent

,PowerConsumption

Ideal:CMOSpowerconsumptionisaboutμW.awayfromthepower-supplyrailP=8.62mW1103.5.4FanoutThenumberofinputsthatthegatecandrivewithoutexceedingitsworst-caseloadingspecifications.在不超出其最坏情况负载规格的条件下，一个逻辑门能驱动的输入端个数。Fanoutmustbeexaminedforbothpossibleoutputstates,HIGNandLOW.

overallfanout=min(HIGH-state,LOW-statefanout)DCfanoutandACfanout111LOWstateFan-OutExample:computethefan-outfor74HCTdriving74LS

HIGHstateFan-OutCMOS:74HCTIOH=–4mAIOL=4mAIIH=1

AIIL=–1

ATTL:74LSIOH=–400

AIOL=8mAIIH=20

AIIL=–0.4mA总扇出

HIGHstate剩余驱动能力：1123.5.5EffectsofLoadingLoadinganoutputbeyonditsrated(额定的)

fanouthasseveraleffects:

(P111)Theoutputvoltagemaydeteriorate.Thepropagationdelay,outputriseandfalltimemayincreasebeyondtheirspecifications.Theoperatingtemperatureofthedevicemayincrease,therebyreducingreliabilityandcausingdevicefailure.1133.5.6UnusedInputsUnusedCMOSinputshouldneverbeleftunconnected(orfloating).XZTodothisincreasethecapacitiveloadonthedrivingsignalandmayslowthingsdown.增加了驱动信号的电容负载，使操作变慢XZ1k+5Vlogic1XZlogic03.5.6HowtodestroyaCMOSdeviceStraycapacitance(寄生电容)Electrostaticdischarge(ESD静电放电)114+-1153.6CMOSDynamicElectricalBehaviorBoththespeedandthepowerconsumptionofaCMOSdevicedependtoalargeextentondynamiccharacteristicsofthedeviceanditsload.Speeddependsontwocharacteristics:TransitionTime

(转换时间)Theamountoftimethattheoutputofalogiccircuittakestochangefromonestatetoanother.PropagationDelay

(传播延迟)Theamountoftimethatittakesforachangeintheinputsignaltoproduceachangeintheoutputsignal.3.6CMOSDynamicElectricalBehaviorStraycapacitance(寄生电容)Jin.UESTC1161173.6.1TransitionTimetrtftrtfHIGHLOWVIHminVILmaxRisetimetrFalltimetf

Tr=

TOHmin-TOLMaxTf=TOLMax-TOHmin1183.6.1TransitionTimeDependontwofactors:“On”resistanceoftransistorcapacitance(电容)VCC=+5.0VRLRpRnVL+CLInrealdigitalcircuit,thetransitiontimeapproximatelyequalstheRCtimeconstant.Fig.3-38计算CMOS的上升和下降时间1193.6.2PropagationDelayVIN50%VOUTSignalpathpropagationdelaytpistheamountoftimethatittakesforachangeintheinputsignaltoproduceachangeintheoutputsignal.Quiz：tr，tf包含在Tp中吗？

50%50%50%1203.6.3PowerConsumptionPT:thepartialshort-circuitingoftheCMOSoutputstructurePL:thecapacitiveloadontheoutputStatic/QuiescentPowerDissipationEitheroneofthetwoMOSTransistorsisoff,ids=ileak

DynamicPowerDissipationVDD=+5.0VVOUTVINTpTnCLPowerdissipationcapacitance功耗电容1213.6.4CurrentSpikesanddecouplingCapacitors电流尖峰和去藕电容器电流传输特性iDvI12VDDCMOS反相器只在PMOS和NMOS管都处于饱和导通状态，才会产生较大的电流，其他情况电流都极小。Jin.UESTC1223.8CMOSLogicFamilies7454PartNumber:

FAMnn

functionHCandHCT(High-speedCMOS,TTLcompatible)Jin.UESTC1233.8CMOSLogicFamiliesAHCandAHCT(A—advanced)*HC（T）*ElectricalCharacteristicsP144Table3-5,P146Table3-6,P147Table3-7Symmetricoutputdrive

(对称的输出驱动) outputcansinkorsourceequalamountsofcurrentACandACTFCTandFCT-TFCT-TElectricalCharacteristicsJin.UESTC1243.9Low-VoltageCMOSLogicandInterfacingWhyLow-Voltage？125电路类型电源电压/V传输延迟时间/ns静态功耗/mW功耗－延迟积/mW-ns直流噪声容限输出逻辑摆幅/VVNL/VVNH/VTTLCT54/74＋510151501.22.23.5CT54LS/74LS＋57.52150.40.53.5HTL＋158530255077.513ECLCE10K系列－5.2225500.1550.1250.8CE100K系列－4.50.7540300.1350.1300.8CMOSVDD=5V＋5455×10－3225×10－32.23.45VDD=15V＋151215×10－3180×10－36.59.015高速CMOS＋581×10－38×10－31.01.55各类数字集成电路主要性能参数的比较126QuizA74LS00hasVOHmin=2.7V,VOLmax=0.5V,VIHmin=2.0V,VILmax=0.8V,determinetheworst-caseLOW-stateandHIGH-stateDCnoisemarginsofthe74LS00.Backups127128Chapter3Task（P175~180）3.1(a)(e)(h)3.2(a)(e)(h)3.53.93.163.173.183.27(d)3.28(自学3.5.8)3.37理解3.393.423.473.49(a)(b)3.57(a)3.53P167Table3-103.56(c)3.613.62

3.81129Chapter3TaskP175~1803.1(a)(e)(h)3.2(a)(e)(h)3.53.93.163.27(d)3.37理解3.393.423.47计算扇出3.49(a)(b)3.57(a)计算直流噪声容限3.533.56(c)选做3.613.623.813.28(自学3.5.8)130DigitalLogicDesignandApplication

Lecture#4Chap.2NumbersystemsandCodesUESTC,Spring2013Introduction所有信息都可以用有限位的二进制数字表示，因此数字系统可以处理任何信息。如何用二进制数字量来表示、运算信息模拟量有正、负之分模拟量有整、零之别除了二进制还有其他表示方法吗不能或不便抽象为两值子集的信息如何处理？131学习要求掌握：十进制、二进制、八进制和十六进制数的表示方法以及它们之间的相互转换、二进制数的运算；符号数的表达：符号-数值码（Signed-MagnitudeSystem、原码），二进制补码(two'scomplement，补码)、二进制反码（ones'complement,反码）表示以及它们之间的相互转换；符号数的运算；溢出的概念。掌握：其他信息的编码表达：BCD码（BinaryCodesforDecimalnumbers）、n中取1码（独热码）、格雷码（Graycode）的特点及其与二进制数之间的转换关系；了解：模拟信息的数字表达：A/D转换的基本概念；了解：字符的代码表示，二进制代码在状态、条件等的表示方面的应用；1322.1PositionalNumbersystem用进位的方法进行计数的数制称为进位计数制(或按位计数制PositionalNumbersystem)。133DigitRadixNumberWeightedsumofthedigits.Weight2.1PositionalNumbersystem134数制的三要素为：数码(digit)：0~r-1，进位规律：逢r进一，借一当r。基数(base/radix)：数码的进制数r，也称为基数（底数）。位权(weight)：ri，数码在一个数中的位置不同，其大小就不同。i是数码所在的位置，称为数位。2.1PositionalNumbersystemDecimal（十进制）Digit：0~9，逢10进1，借1当10Weight：(10)10

iRadix：10

2.1PositionalNumbersystemBinary

(二进制)Digit：0~1，逢2进1，借一当2Weight：(2)10

iRadix：2二进制的优点：运算简单，电路简单，工作可靠。数字电路中多使用二进制.二进制的不足：一个较大的十进制用二进制表示需要较多的位，为了克服二进制书写太长的缺点，常用八进制和十六进制。2.1PositionalNumbersystemOctal（八进制）Digit：0~7，逢8进1，借1当8Weight：(8)10

iRadix：8

Hexadecimal（十六进制）Digit：0~9A~F（10~15)，逢16进1，借1当16Weight：(16)10

i