《数字电子技术与接口技术试验教程》课件第6章

第6章数字钟和频率计设计

6.1数字钟设计6.2数字频率计

6.1数 字 钟 设 计

数字钟设计的关键在于产生秒脉冲、对秒脉冲计数并产生分和小时以及动态显示时、分、秒信息。

实验要求：

(1)在开发板上运行有关程序。

(2)设计一个完整的数字钟，小时和分钟用数码管显示，秒用发光二极管闪烁显示，每秒闪烁一次。如有可能，请增加校时功能。

Basys2板上只有4个数码管，因此这里只设计了一个秒和分计时时钟。6.1.1采用8421BCD码计数的Verilog时钟程序

下面是采用8421BCD计数，并在一个模块中实现时钟功能的Verilog程序。时钟程序比较简单，可以用一个模块直接实现。由主时钟(50MHz)分频得到秒信号，计秒到60时分加1，秒清零，计分到60时，分清零。请读者分析，为什么程序从表面上看秒和分都是计到59时就清零了，而不是计到60再清零。

moduleClock_Sec_Min_disp(

inputwireclk,

inputwireclr,

outputSecond_Flash,

outputreg[6:0]a_to_g,

outputreg[3:0]an

);

//中间变量定义

reg[3:0]LED0_num,LED1_num,LED2_num,LED3_num;

reg[1:0]s;

reg[3:0]digit;

reg[16:0]clkdiv; //(1FFFF)*20ns=2.6ms

reg[26:0]q1; //设一足够长的计数器

regsec;

reg[3:0]Second_L;

reg[3:0]Second_H;

reg[3:0]Minute_L;

reg[3:0]Minute_H;

//初始化

initialbegin

Second_L=5;

Second_H=5;

Minute_L=8;

Minute_H=5;

LED3_num=Second_L;

LED2_num=Second_H;

LED1_num=Minute_L;

LED0_num=Minute_H;

end

//动态数码管扫描显示

always@(*)

begin

an=4'b1111; //禁止所有数码管显示

s<=clkdiv[16:15];//间隔2.6ms使能An

an[s]=0;//根据s使能数码管其中之一

case(s)//根据s取对应的数码管上要显示的数据

0:digit<=LED0_num[3:0];

1:digit<=LED1_num[3:0];

2:digit<=LED2_num[3:0];

3:digit<=LED3_num[3:0];

default:digit<=LED3_num[3:0];

endcase

case(digit) //七段译码表

0:a_to_g=7'b0000001;

1:a_to_g=7'b1001111;

2:a_to_g=7'b0010010;

3:a_to_g=7'b0000110;

4:a_to_g=7'b1001100;

5:a_to_g=7'b0100100;

6:a_to_g=7'b0100000;

7:a_to_g=7'b0001111;

8:a_to_g=7'b0000000;

9:a_to_g=7'b0000100;

'hA:a_to_g=7'b0001000;

'hB:a_to_g=7'b1100000;

'hC:a_to_g=7'b0110001;

'hD:a_to_g=7'b1000010;

'hE:a_to_g=7'b0110000;

'hF:a_to_g=7'b0111000;

default:a_to_g=7'b0000001;//0

endcase

end

//主时钟计数:50MHz时钟，周期20ns，计数到1FFFFh时长2621420ns，约2.6ms

always@(posedgeclk)

begin

clkdiv<=clkdiv+1;

end

//时钟程序：计数到50000000为1s，计秒得分

always@(posedgeclkorposedgeclr)

begin

if(clr==1)

begin

q1<=0;

LED0_num=0;

LED1_num=0;

LED2_num=0;

LED3_num=0;

Second_L<=0;

Second_H<=0;

Minute_L<=0;

Minute_H<=0;

end

elseif(q1==50000000)

begin

q1<=0;

sec=~sec;

LED3_num[3:0]=Second_L[3:0];

LED2_num[3:0]=Second_H[3:0];

LED1_num[3:0]=Minute_L[3:0];

LED0_num[3:0]=Minute_H[3:0];

Second_L<=Second_L+1;

if(Second_L==9)

begin

Second_L<=0;

Second_H<=Second_H+1;

end

if(Second_H==5&&Second_L==9)

begin

Second_L<=0;

Second_H<=0;

Minute_L<=Minute_L+1;

if(Minute_L==9)

begin

Minute_L<=0;

Minute_H<=Minute_H+1;

end

if(Minute_H==5&&Minute_L==9)

begin

Minute_L<=0;

Minute_H<=0;

end

end

end

else

q1<=q1+1;

end

assignSecond_Flash=sec;//1Hz

endmodule约束文件如下：

#Basys2约束文件：

NET“a_to_g[0]”LOC=M12;

NET“a_to_g[1]”LOC=L13;

NET“a_to_g[2]”LOC=P12;

NET“a_to_g[3]”LOC=N11;

NET“a_to_g[4]”LOC=N14;

NET“a_to_g[5]”LOC=H12;

NET“a_to_g[6]”LOC=L14;

NET“an[0]”LOC=K14;

NET"an[1]"LOC=M13;

NET"an[2]"LOC=J12;

NET"an[3]"LOC=F12;

NET"clk"LOC="B8"; //50MHz时钟

NET"clr"LOC="P11"; //SW0

NET"Second_Flash"LOC="M5"; //LD06.1.2采用模块化设计Verilog时钟程序

在数字系统中一般采用自上而下的设计方法，将系统分成若干个功能模块，模块还可继续向下划分成子模块，直至分成许多最基本的功能模块。

下面将时钟程序分为秒脉冲发生模块、秒60进制模块、分60进制模块以及动态数码管显示模块。秒60进制模块和分60进制模块的程序是一样的。一个模块设计好后，可以在顶层模块中多次使用，只要改变该模块例化后的模块名称，并给出其相应的输入输出连接即可。

//顶层设计：

moduleClock_top(

inputwireclk,

inputwireclr,

outputSecond_Flash,

output[6:0]a_to_g,

output[3:0]an

);

//模块间连接定义(注意必须是wire)

wire[3:0]Second_L;

wire[3:0]Second_H;

wire[3:0]Minute_L;

wire[3:0]Minute_H;

wirejinwei;

SecondPulseU0(

.clk(clk),

.clr(clr),

.sec(Second_Flash)

);

cnt60U1(

.clk(Second_Flash),

.clr(clr),

.cnt60_L(Second_L),

.cnt60_H(Second_H),

.carry(jinwei)

);

cnt60U2(

.clk(jinwei),

.clr(clr),

.cnt60_L(Minute_L),

.cnt60_H(Minute_H),

.carry(carry)

);

dispU3(

.clk(clk),

.LED0_num(Second_L),

.LED1_num(Second_H),

.LED2_num(Minute_L),

.LED3_num(Minute_H),

.a_to_g(a_to_g),

.an(an)

);

endmodule

//秒脉冲发生模块：

moduleSecondPulse(

inputwireclk,

inputwireclr,

outputregsec

);

//中间变量定义

reg[26:0]q1;//设一足够长的计数器

//时钟程序：计数到25000000输出sec翻转一次，翻转两次为1s

always@(posedgeclkorposedgeclr)

begin

if(clr==1)

q1<=0;

elseif(q1==25000000)

begin

q1<=0;

sec=~sec;

end

else

q1<=q1+1;

end

endmodule

//60进制计数模块：

modulecnt60(

inputwireclk,

inputwireclr,

outputreg[3:0]cnt60_L,

outputreg[3:0]cnt60_H,

outputregcarry

);

//初始化

initialbegin

cnt60_L=8;

cnt60_H=5;

end

//60进制计数器

always@(posedgeclkorposedgeclr)

begin

if(clr==1)

begin

cnt60_L<=0;

cnt60_H<=0;

end

else

begin

carry<=0;

cnt60_L<=cnt60_L+1;

if(cnt60_L==9)

begin

cnt60_L<=0;

cnt60_H<=cnt60_H+1;

end

if(cnt60_H==5&&cnt60_L==9)

begin

cnt60_L<=0;

cnt60_H<=0;

carry<=1;

end

end

end

endmodule

//数码管动态显示模块：

moduledisp(

inputwireclk,

input[3:0]LED0_num,

input[3:0]LED1_num,

input[3:0]LED2_num,

input[3:0]LED3_num,

outputreg[6:0]a_to_g,

outputreg[3:0]an

);

//中间变量定义

reg[1:0]s;

reg[3:0]digit;

reg[16:0]clkdiv;//(1FFFF)*20ns=2.6ms

//动态数码管扫描显示

always@(*)

begin

an=4'b1111; //禁止所有数码管显示

s<=clkdiv[16:15];//间隔2.6ms使能An

an[s]=0; //根据s使能数码管其中之一

case(s)//根据s取对应的数码管上要显示的数据

0:digit<=LED0_num[3:0];

1:digit<=LED1_num[3:0];

2:digit<=LED2_num[3:0];

3:digit<=LED3_num[3:0];

default:digit<=LED3_num[3:0];

endcase

case(digit) //七段译码表

0:a_to_g=7'b0000001;

1:a_to_g=7'b1001111;

2:a_to_g=7'b0010010;

3:a_to_g=7'b0000110;

4:a_to_g=7'b1001100;

5:a_to_g=7'b0100100;

6:a_to_g=7'b0100000;

7:a_to_g=7'b0001111;

8:a_to_g=7'b0000000;

9:a_to_g=7'b0000100;

'hA:a_to_g=7'b0001000;

'hB:a_to_g=7'b1100000;

'hC:a_to_g=7'b0110001;

'hD:a_to_g=7'b1000010;

'hE:a_to_g=7'b0110000;

'hF:a_to_g=7'b0111000;

default:a_to_g=7'b0000001;//0

endcase

end

//主时钟计数:50MHz时钟，周期20ns，计数到1FFFFh时长2621420ns，约2.6ms

always@(posedgeclk)

begin

clkdiv<=clkdiv+1;

end

endmodule

#Basys2约束文件：

NET"a_to_g[0]"LOC=M12;

NET"a_to_g[1]"LOC=L13;

NET"a_to_g[2]"LOC=P12;

NET"a_to_g[3]"LOC=N11;

NET“a_to_g[4]”LOC=N14;

NET“a_to_g[5]”LOC=H12;

NET“a_to_g[6]”LOC=L14;

NET“an[3]”LOC=K14;

NET“an[2]”LOC=M13;

NET“an[1]”LOC=J12;

NET“an[0]”LOC=F12;

NET“clk”LOC=“B8”; // 50 MHz时钟

NET“clr”LOC=“P11”;// SW0

NET"Second_Flash"LOC="M5";// LD0

图6-1为VerilogHDL设计的数字钟的顶层原理图。图6-1用VerilogHDL设计的数字钟的顶层原理图

6.1.3采用状态机设计动态数码管显示的时钟VHDL程序

下面的时钟VHDL程序分为BCD码计时模块和动态数码管显示模块。采用状态机法设计动态数码管显示。显示模块先将输入的十进制数的个位译码，加在七段数码管的段控制线上，在显示扫描时钟的作用下，选通个位上的数码管，个位上的数码管亮，其他数码管灭。然后输出十位上数码管要显示的内容，选通十位上的数码管。这样依次输出各位的译码值，逐个选通数码管。由于扫描频率为1kHz，看起来不会有闪烁的感觉。

--顶层设计：

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_unsigned.all;

entityClock_topis

Port(StdClock:inSTD_LOGIC;

Second_Flash:outSTD_LOGIC;

Segments:outSTD_LOGIC_VECTOR(7downto0);

Position:outSTD_LOGIC_VECTOR(3downto0));

endClock_top;

architectureBehavioralofClock_topis

COMPONENTClock_Counter

PORT(

StdClock:INstd_logic;

Second_Flash:OUTstd_logic;

Counter32_16:OUTstd_logic_vector(15downto0)

);

ENDCOMPONENT;

COMPONENTDynamic_Display

PORT(

StdClock:INstd_logic;

DataInput:INstd_logic_vector(15downto0);

Segments:OUTstd_logic_vector(7downto0);

Position:OUTstd_logic_vector(3downto0)

);

ENDCOMPONENT;

signalCounter32_tmp:STD_LOGIC_VECTOR(15downto0);

begin

Inst_Clock_Counter:Clock_CounterPORTMAP(

StdClock=>StdClock,

Second_Flash=>Second_Flash,

Counter32_16=>Counter32_tmp

);

Inst_Dynamic_Display:Dynamic_DisplayPORTMAP(

StdClock=>StdClock,

DataInput=>Counter32_tmp,

Segments=>Segments,

Position=>Position

);

endBehavioral;

--计时模块：

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_unsigned.all;

entityClock_Counteris

Port(StdClock:inSTD_LOGIC;

Second_Flash:outSTD_LOGIC;

Counter32_16:outSTD_LOGIC_VECTOR(15downto0));

endClock_Counter;

architectureBehavioralofClock_Counteris

---信号定义

signalcounter25_reg:STD_LOGIC_VECTOR(25downto0);

signalSecond_L:STD_LOGIC_VECTOR(3downto0):="0101";

signalSecond_H:STD_LOGIC_VECTOR(3downto0):="0101";

signalMintue_L:STD_LOGIC_VECTOR(3downto0):="1000";

signalMintue_H:STD_LOGIC_VECTOR(3downto0):="0101";

begin

process(StdClock)

begin

ifrising_edge(StdClock)then

ifcounter25_reg<50000000then--f = 50MHz,T = 20ns,50000000×20ns = 1s

counter25_reg<=counter25_reg+1;

else

counter25_reg<="00000000000000000000000000";

Second_L<=Second_L+1;

ifSecond_L=9then

Second_L<="0000";

Second_H<=Second_H+1;

endif;

ifSecond_H=5andSecond_L=9then

Second_L<="0000";

Second_H<="0000";

Mintue_L<=Mintue_L+1;

ifMintue_L=9then

Mintue_L<="0000";

Mintue_H<=Mintue_H+1;

endif;

ifMintue_H=5andMintue_L=9then

Mintue_L<="0000";

Mintue_H<="0000";

endif;

endif;

endif;

endif;

endprocess;

Counter32_16(3downto0)<=Second_L;

Counter32_16(7downto4)<=Second_H;

Counter32_16(11downto8)<=Mintue_L;

Counter32_16(15downto12)<=Mintue_H;

Second_Flash<=counter25_reg(25);--50000000 = 2FAF080H

endBehavioral;

--采用状态机设计的动态数码管显示模块：

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

entityDynamic_Displayis

Port(StdClock:inSTD_LOGIC;

DataInput:inSTD_LOGIC_VECTOR(15downto0);

Segments:outSTD_LOGIC_VECTOR(7downto0);

Position:outSTD_LOGIC_VECTOR(3downto0));

endDynamic_Display;

architectureBehavioralofDynamic_Displayis

---状态机定义

typestate_typeis(led1,led2,led3,led4);

signalnext_state:state_type;

---信号定义

signalclk1KHz_reg:STD_LOGIC;

signalScanClock_reg:STD_LOGIC;

signaldatacut_reg:STD_LOGIC_VECTOR(3downto0):="0000";

signaldatacut_reg2:STD_LOGIC_VECTOR(3downto0):="0000";

signaldatacut_reg3:STD_LOGIC_VECTOR(3downto0):="0000";

signaldatacut_reg4:STD_LOGIC_VECTOR(3downto0):="0000";

signalposition_reg:STD_LOGIC_VECTOR(3downto0):="1110";

signalsegments_reg:STD_LOGIC_VECTOR(7downto0):="00000000";

---signalDataInput:STD_LOGIC_VECTOR(15downto0):="0101011001111000";---显示5678

----------------------------------------

begin

---由50MHz标准时钟信号分频得到1kHz显示扫描信号

Clk1KHz_Proc:process(StdClock)

variablecnt1:integerrange0to24999;

begin

ifrising_edge(StdClock)then

ifcnt1=24999then

cnt1:=0;

clk1KHz_reg<=notclk1KHz_reg;

else

cnt1:=cnt1+1;

endif;

endif;

endprocess;

ScanClock_reg<=clk1KHz_reg;

---数码管选择处理

Position_Process:process(ScanClock_reg)

begin

ifrising_edge(ScanClock_reg)then

casenext_stateis

---第一个数码管亮

whenled1=>

position_reg<="1110";

datacut_reg<=DataInput(3downto0);

next_state<=led2;

---第二个数码管亮

whenled2=>

position_reg<="1101";

datacut_reg2<=DataInput(7downto4);

datacut_reg<=datacut_reg2;

next_state<=led3;

---第三个数码管亮

whenled3=>

position_reg<="1011";

datacut_reg3<=DataInput(11downto8);

datacut_reg<=datacut_reg3;

next_state<=led4;

---第四个数码管亮

whenled4=>

position_reg<="0111";

datacut_reg4<=DataInput(15downto12);

datacut_reg<=datacut_reg4;

next_state<=led1;

---所有数码管全灭

whenothers=>

position_reg<="0000";

datacut_reg<="1100";

next_state<=led1;

endcase;

endif;

endprocess;

withdatacut_regselect

segments_reg<="10000001"when"0000",---0

"11001111"when"0001",---1

"10010010"when"0010",---2

"10000110"when"0011",---3

"11001100"when"0100",---4

"10100100"when"0101",---5

"10100000"when"0110",---6

"10001111"when"0111",---7

"10000000"when"1000",---8

"10000100"when"1001",---9

"10001000"when"1010",---A

"11100000"when"1011",---B

"10110001"when"1100",---C

"11000010"when"1101",---D

"10110000"when"1110",---E

"10111000"when"1111",---F

"11111111"whenothers;---F.

segments<=segments_reg;

position<=position_reg;

endBehavioral;

#Basys2约束文件：

NET"StdClock"LOC="B8"; //50MHz系统标准时钟引脚

NET"Segments[0]"LOC="M12"; //G

NET"Segments[1]"LOC="L13"; //F

NET"Segments[2]"LOC="P12"; //E

NET"Segments[3]"LOC="N11"; //D

NET"Segments[4]"LOC="N14"; //C

NET"Segments[5]"LOC="H12"; //B

NET“Segments[6]”LOC=“L14”; //A

NET“Segments[7]”LOC=“N13”; //dp

NET“Position[0]”LOC=“F12”; //AN0

NET“Position[1]”LOC=“J12”; //AN1

NET“Position[2]”LOC=“M13”; //AN2

NET“Position[3]”LOC=“K14”; //AN3

NET“Second_Flash”LOC=“M5”; //LD0

用状态机设计的数字钟的顶层原理图如图6-2所示。图6-2用状态机设计的数字钟的顶层图6.1.4采用六十进制计时模块设计的VHDL时钟程序

下面的时钟VHDL程序由顶层设计、时钟分频模块、六十进制计数器、以及显示模块组成。六十进制模块程序例化后，可在顶层设计中多次使用。这里的秒计数器和分计数器都采用的是六十进制计数器的程序。一个VHDL模块例化后，在其模板中有两部分，一部分是COMPONENT(元件)描述部分，另一部分是PORTMAP(端口映射)描述部分。将这两部分拷贝到顶层模块中，只要根据需要进行端口映射(也就是端口连接)即可。

--顶层设计：

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

entityclock_sec_min_dispis

Port(clk:inSTD_LOGIC;

clr:inSTD_LOGIC;

second_flash:inoutSTD_LOGIC;

a_to_g:outSTD_LOGIC_VECTOR(6downto0);

an:outSTD_LOGIC_VECTOR(3downto0));

endclock_sec_min_disp;

architectureBehavioralofclock_sec_min_dispis

componentclkdivis

Port(clk:inSTD_LOGIC;

clr:inSTD_LOGIC;

clkout:outSTD_LOGIC);

endcomponent;

componentcnt60is

Port(clk:inSTD_LOGIC;

clr:inSTD_LOGIC;

cnt60_h:outSTD_LOGIC_VECTOR(3downto0);

cnt60_l:outSTD_LOGIC_VECTOR(3downto0);

qc:outSTD_LOGIC);

endcomponent;

componentdisplayis

Port(c60_1_h:inSTD_LOGIC_VECTOR(3downto0);

c60_1_l:inSTD_LOGIC_VECTOR(3downto0);

c60_2_h:inSTD_LOGIC_VECTOR(3downto0);

c60_2_l:inSTD_LOGIC_VECTOR(3downto0);

clk:inSTD_LOGIC;

clr:inSTD_LOGIC;

a_to_g:outSTD_LOGIC_VECTOR(6downto0);

an:outSTD_LOGIC_VECTOR(3downto0));

endcomponent;

signalmclk,qc1,qc2:std_logic;

signalc6011,c6012,c6021,c6022:std_logic_vector(3downto0);

begin

c_div:clkdiv

portmap(clk,clr,mclk);

process(mclk,clr)

begin

if(clr='1')then

second_flash<='0';

elsif(mclk'eventandmclk='1')then

second_flash<=notsecond_flash;

endif;

endprocess;

c_601:cnt60

portmap(mclk,clr,c6011,c6012,qc1);

c_602:cnt60

portmap(qc1,clr,c6021,c6022,qc2);

c_display:display

portmap(c6011,c6012,c6021,c6022,clk,clr,a_to_g,an);

endBehavioral;

--时钟分频模块：

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_arith.ALL;

useIEEE.STD_LOGIC_unsigned.ALL;

entityclkdivis

Port(clk:inSTD_LOGIC;

clr:inSTD_LOGIC;

clkout:outSTD_LOGIC);

endclkdiv;

architectureBehavioralofclkdivis

signalq1:std_logic_vector(24downto0);

begin

process(clk,clr)

begin

if(clr='1')then

q1<="0000000000000000000000000";

elsif(clk'eventandclk='1')then

q1<=q1+1;

endif;

endprocess;

clkout<=q1(24);

endBehavioral;

--60进制计数模块：

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_arith.ALL;

useIEEE.STD_LOGIC_unsigned.ALL;

entitycnt60is

Port(clk:inSTD_LOGIC;

clr:inSTD_LOGIC;

cnt60_h:inoutSTD_LOGIC_VECTOR(3downto0);

cnt60_l:inoutSTD_LOGIC_VECTOR(3downto0);

qc:outSTD_LOGIC);

endcnt60;

architectureBehavioralofcnt60is

begin

process(clr,clk)

begin

if(clr='1')then

cnt60_h<="0000";

cnt60_l<="0000";

elsif(clk'eventandclk='1')then

qc<='0';

if(cnt60_l="1001")then

cnt60_l<="0000";

cnt60_h<=cnt60_h+1;

else

cnt60_l<=cnt60_l+1;

endif;

if(cnt60_l="1001"andcnt60_h="0101")then

cnt60_l<="0000";

cnt60_h<="0000";

qc<='1';

endif;

endif;

endprocess;

endBehavioral;

--显示模块：

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_arith.ALL;

useIEEE.STD_LOGIC_unsigned.ALL;

entitydisplayis

Port(c60_1_h:inSTD_LOGIC_VECTOR(3downto0);

c60_1_l:inSTD_LOGIC_VECTOR(3downto0);

c60_2_h:inSTD_LOGIC_VECTOR(3downto0);

c60_2_l:inSTD_LOGIC_VECTOR(3downto0);

clk:inSTD_LOGIC;

clr:inSTD_LOGIC;

a_to_g:outSTD_LOGIC_VECTOR(6downto0);

an:outSTD_LOGIC_VECTOR(3downto0));

enddisplay;

architectureBehavioralofdisplayis

signalclksweep:std_logic_vector(19downto0);

signals:std_logic_vector(1downto0);

signaldigit:std_logic_vector(3downto0);

begin

process(clk,clr)

begin

if(clr='1')then

clksweep<="00000000000000000000";

elsif(clk'eventandclk='1')then

clksweep<=clksweep+1;

endif;

endprocess;

s<=clksweep(19downto18);

process(s,c60_1_h,c60_1_l,c60_2_h,c60_2_l)

begin

casesis

when"00"=>an<="1110";digit<=c60_2_h;

when"01"=>an<="1101";digit<=c60_2_l;

when"10"=>an<="1011";digit<=c60_1_h;

when"11"=>an<="0111";digit<=c60_1_l;

whenothers=>null;

endcase;

endprocess;

process(digit)

begin

casedigitis

when"0000"=>a_to_g<="0000001";

when"0001"=>a_to_g<="1001111";

when"0010"=>a_to_g<="0010010";

when"0011"=>a_to_g<="0000110";

when"0100"=>a_to_g<="1001100";

when"0101"=>a_to_g<="0100100";

when"0110"=>a_to_g<="0100000";

when"0111"=>a_to_g<="0001111";

when"1000"=>a_to_g<="0000000";

when"1001"=>a_to_g<="0000100";

when"1010"=>a_to_g<="0001000";

when"1011"=>a_to_g<="1100001";

when"1100"=>a_to_g<="0110001";

when"1101"=>a_to_g<="1000010";

when"1110"=>a_to_g<="0110000";

when"1111"=>a_to_g<="0111000";

whenothers=>a_to_g<="0000001";

endcase;

endprocess;

endBehavioral;

#Basys2约束文件：

NET"a_to_g[0]"LOC=M12;

NET"a_to_g[1]"LOC=L13;

NET"a_to_g[2]"LOC=P12;

NET“a_to_g[3]”LOC=N11;

NET“a_to_g[4]”LOC=N14;

NET“a_to_g[5]”LOC=H12;

NET“a_to_g[6]”LOC=L14;

NET“an[0]”LOC=K14;

NET“an[1]”LOC=M13;

NET“an[2]”LOC=J12;

NET“an[3]”LOC=F12;

NET“clk”LOC=“B8”; //50