并行乘法器-南京理工大学紫金学院vhdl实验报告-eda

EDA技术与应用实验报告实验名称：并行乘法器姓名：学号：班级：通信时间：2013南京理工大学紫金学院电光系实验目的1、学习包集和元件例化语句的使用。2、学习FLU（全加器单元）电路的设计。3、学习并行乘法电路的设计。实验原理并行乘法器的电路原理图如下图所示，主要由全加器和与门构成。并行乘法器原理图实验内容and_2libraryieee;useieee.std_logic_1164.all;entityand_2is port(a,b:instd_logic; y:outstd_logic);endand_2;architectureand_2ofand_2isbegin y<=aandb; endand_2;componentlower_rowis port(sin,cin:instd_logic_vector(2downto0); p:outstd_logic_vector(3downto0));endcomponent;endmy_components;multiplierlibraryieee;useieee.std_logic_1164.all;usework.my_components.all;entitymultiplieris port(a,b:instd_logic_vector(3downto0); prod:outstd_logic_vector(7downto0));endmultiplier;architecturestructuralofmultiplieris typematrixisarray(0to3)of std_logic_vector(2downto0); signals,c:matrix;begin U1:componenttop_rowportmap(a(0),b,s(0),c(0), prod(0)); U2:componentmid_rowportmap(a(1),b,s(0),c(0),s(1), c(1),prod(1)); U3:componentmid_rowportmap(a(2),b,s(1),c(1),s(2), c(2),prod(2)); U4:componentmid_rowportmap(a(3),b,s(2),c(2),s(3), c(3),prod(3)); U5:componentlower_rowportmap(s(3),c(3), prod(7downto4));endstructural;8、仿真9、把multiplier代码改为百位、十位、个位输出代码如下：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;usework.my_components.all;entitymultiplieris port(a,b:instd_logic_vector(3downto0); hun,ten,one:outstd_logic_vector(3downto0));endmultiplier;architecturestructuralofmultiplieris typematrixisarray(0to3)of std_logic_vector(2downto0); signals,c:matrix; signalp:std_logic_vector(7downto0);begin U1:componenttop_rowportmap(a(0),b,s(0),c(0), p(0)); U2:componentmid_rowportmap(a(1),b,s(0),c(0),s(1), c(1),p(1)); U3:componentmid_rowportmap(a(2),b,s(1),c(1),s(2), c(2),p(2)); U4:componentmid_rowportmap(a(3),b,s(2),c(2),s(3), c(3),p(3)); U5:componentlower_rowportmap(s(3),c(3), p(7downto4));process(p)variabletemp:std_logic_vector(7downto0);begin ifp>"1100_0111"then hun<="0010"; temp:=p-"1100_1000"; elsifp>"0110_0011"then hun<="0001"; temp:=p-"0110_0100"; else hun<="0000"; temp:=p; endif; iftemp>"0101_1001"then ten<="1001"; temp:=temp-"0101_1010"; elsiftemp>"0100_1111"then ten<="1000"; temp:=temp-"1010_0000"; elsiftemp>"0100_0101"then ten<="0111"; temp:=temp-"0100_0110"; elsiftemp>"0011_1011"then ten<="0110"; temp:=temp-"0011_1100"; elsiftemp>"0011_0001"then ten<="0101"; temp:=temp-"0011_0010"; elsiftemp>"0010_0111"then ten<="0100"; temp:=temp-"0010_1000"; elsiftemp>"0001_1101"then ten<="0011"; temp:=temp-"0001_1110"; elsiftemp>"0001_0011"then ten<="0010"; temp:=temp-"0001_0100"; elsiftemp>"0000_1001"then ten<="0001"; temp:=temp-"00