文库发布：cmosvlsi设计课件

Lecture1:

Circuits&Layout11:Circuits&LayoutOutlineABriefHistoryCMOSGateDesignPassTransistorsCMOSLatches&Flip-FlopsStandardCellLayoutsStickDiagrams21:Circuits&LayoutABriefHistory1958:FirstintegratedcircuitFlip-flopusingtwotransistorsBuiltbyJackKilbyatTexasInstruments2010IntelCorei7mprocessor

2.3billiontransistors64GbFlashmemory>16billiontransistorsCourtesyTexasInstruments[Trinh09]©2009IEEE.31:Circuits&LayoutGrowthRate53%compoundannualgrowthrateover50yearsNoothertechnologyhasgrownsofastsolongDrivenbyminiaturizationoftransistorsSmallerischeaper,faster,lowerinpower!Revolutionaryeffectsonsociety[Moore65]ElectronicsMagazine41:Circuits&LayoutAnnualSales>1019transistorsmanufacturedin20081billionforeveryhumanontheplanet51:Circuits&LayoutInventionoftheTransistorVacuumtubesruledinfirsthalfof20thcenturyLarge,expensive,power-hungry,unreliable1947:firstpointcontacttransistorJohnBardeenandWalterBrattainatBellLabsSeeCrystalFire byRiordan,HoddesonAT&TArchives.Reprintedwithpermission.61:Circuits&LayoutTransistorTypesBipolartransistorsnpnorpnpsiliconstructureSmallcurrentintoverythinbaselayercontrolslargecurrentsbetweenemitterandcollectorBasecurrentslimitintegrationdensityMetalOxideSemiconductorFieldEffectTransistorsnMOSandpMOSMOSFETSVoltageappliedtoinsulatedgatecontrolscurrentbetweensourceanddrainLowpowerallowsveryhighintegration71:Circuits&Layout1970’sprocessesusuallyhadonlynMOStransistorsInexpensive,butconsumepowerwhileidle1980s-present:CMOSprocessesforlowidlepowerMOSIntegratedCircuitsIntel1101256-bitSRAMIntel40044-bitmProc[Vadasz69]©1969IEEE.IntelMuseum.Reprintedwithpermission.81:Circuits&LayoutMoore’sLaw:Then1965:GordonMooreplottedtransistoroneachchipFitstraightlineonsemilogscaleTransistorcountshavedoubledevery26monthsIntegrationLevelsSSI: 10gatesMSI: 1000gatesLSI: 10,000gatesVLSI: >10kgates[Moore65]ElectronicsMagazine91:Circuits&LayoutAndNow…101:Circuits&LayoutFeatureSizeMinimumfeaturesizeshrinking30%every2-3years111:Circuits&LayoutCorollariesManyotherfactorsgrowexponentiallyEx:clockfrequency,processorperformance121:Circuits&LayoutCMOSGateDesignActivity:Sketcha4-inputCMOSNORgate131:Circuits&LayoutComplementaryCMOSComplementaryCMOSlogicgatesnMOSpull-downnetworkpMOSpull-upnetworka.k.a.staticCMOSPull-upOFFPull-upONPull-downOFFZ(float)1Pull-downON0X(crowbar)141:Circuits&LayoutSeriesandParallelnMOS:1=ONpMOS:0=ONSeries:bothmustbeONParallel:eithercanbeON151:Circuits&LayoutConductionComplementComplementaryCMOSgatesalwaysproduce0or1Ex:NANDgateSeriesnMOS:Y=0whenbothinputsare1ThusY=1wheneitherinputis0RequiresparallelpMOSRuleofConductionComplementsPull-upnetworkiscomplementofpull-downParallel->series,series->parallel161:Circuits&LayoutCompoundGatesCompoundgatescandoanyinvertingfunctionEx:171:Circuits&LayoutExample:O3AI

181:Circuits&LayoutSignalStrengthStrengthofsignalHowcloseitapproximatesidealvoltagesourceVDDandGNDrailsarestrongest1and0nMOSpassstrong0Butdegradedorweak1pMOSpassstrong1Butdegradedorweak0ThusnMOSarebestforpull-downnetwork191:Circuits&LayoutPassTransistorsTransistorscanbeusedasswitches201:Circuits&LayoutTransmissionGatesPasstransistorsproducedegradedoutputsTransmissiongatespassboth0and1well211:Circuits&LayoutTristatesTristatebufferproducesZwhennotenabledENAY00Z01Z100111221:Circuits&LayoutNonrestoringTristateTransmissiongateactsastristatebufferOnlytwotransistorsButnonrestoringNoiseonAispassedontoY231:Circuits&LayoutTristateInverterTristateinverterproducesrestoredoutputViolatesconductioncomplementruleBecausewewantaZoutput241:Circuits&LayoutMultiplexers2:1multiplexerchoosesbetweentwoinputsSD1D0Y0X000X1110X011X1251:Circuits&LayoutGate-LevelMuxDesign

Howmanytransistorsareneeded?20261:Circuits&LayoutTransmissionGateMuxNonrestoringmuxusestwotransmissiongatesOnly4transistors271:Circuits&LayoutInvertingMuxInvertingmultiplexerUsecompoundAOI22OrpairoftristateinvertersEssentiallythesamethingNoninvertingmultiplexeraddsaninverter281:Circuits&Layout4:1Multiplexer4:1muxchoosesoneof4inputsusingtwoselectsTwolevelsof2:1muxesOrfourtristates291:Circuits&LayoutDLatchWhenCLK=1,latchistransparentDflowsthroughtoQlikeabufferWhenCLK=0,thelatchisopaqueQholdsitsoldvalueindependentofDa.k.a.transparentlatchorlevel-sensitivelatch301:Circuits&LayoutDLatchDesignMultiplexerchoosesDoroldQ311:Circuits&LayoutDLatchOperation321:Circuits&LayoutDFlip-flopWhenCLKrises,DiscopiedtoQAtallothertimes,Qholdsitsvaluea.k.a.positiveedge-triggeredflip-flop,master-slaveflip-flop331:Circuits&LayoutDFlip-flopDesignBuiltfrommasterandslaveDlatches341:Circuits&LayoutDFlip-flopOperation351:Circuits&LayoutRaceConditionBack-to-backflopscanmalfunctionfromclockskewSecondflip-flopfireslateSeesfirstflip-flopchangeandcapturesitsresultCalledhold-timefailureorracecondition361:Circuits&LayoutNonoverlappingClocksNonoverlappingclockscanpreventracesAslongasnonoverlapexceedsclockskewWewillusetheminthisclassforsafedesignIndustrymanagesskewmorecarefullyinstead371:Circuits&LayoutGateLayoutLayoutcanbeverytimeconsumingDesigngatestofittogethernicelyBuildalibraryofstandardcellsStandardcelldesignmethodologyVDDandGNDshouldabut(standardheight)AdjacentgatesshouldsatisfydesignrulesnMOSatbottomandpMOSattopAllgatesincludewellandsubstratecontacts381:Circuits&LayoutExample:Inverter391:Circuits&LayoutExample:NAND3HorizontalN-diffusionandp-diffusionstripsVerticalpolysilicongatesMetal1VDDrailattopMetal1GNDrailatbottom32lby40