基于FPGA的恒虚警(CFAR)算法

基于FPGA的恒虚警（CFAR）算法设计与实现作者:学号：学院(系):电子工程与光电技术学院专业:电磁场与微波技术题目:基于FPGA的恒虚警（CFAR）算法设计与实现指导老师：日期：2015年10月TOC\o"1-3"\h\u 30745摘要 1292171引言 2305722CFAR算法原理与算法模型 3104872.1ML类CFAR 3189772.2OS类CFAR 592193CA-CFAR算法设计与实现 7121633.1CFAR的VerilogHDL设计 925467总结 206458致谢 2117010参考文献 22③详细设计：CFAR.v：moduleCFAR( I_rst_n , I_clk , I_noise , I_signal , O_result); input I_rst_n ;input I_clk ;input[15:0] I_noise ;input[15:0] I_signal ;output[15:0] O_result ;reg[15:0] O_result ;reg[15:0] R_noise ;reg[15:0] R1_noise ;reg[15:0] R2_noise ;reg[15:0] R3_noise ;reg[15:0] R4_noise ;reg[15:0] R5_noise ;reg[15:0] R6_noise ;reg[15:0] R7_noise ;reg[15:0] R8_noise ;reg[15:0] R9_noise ;reg[15:0] R10_noise ;reg[15:0] R11_noise ;reg[15:0] R12_noise ;reg[15:0] R13_noise ;reg[15:0] R14_noise ;reg[19:0] R_add ;reg[15:0] R1_add ;reg[15:0] R2_add ;reg[15:0] R3_add ;reg[15:0] R4_add ;reg[15:0] R5_add ;reg[15:0] R6_add ;reg[15:0] R7_add ;reg[15:0] R8_add ;reg[15:0] R9_add ;reg[15:0] R10_add ;reg[15:0] R11_add ;reg[15:0] R12_add ;reg[15:0] R13_add ;reg[15:0] R14_add ;reg[15:0] R15_add ;reg[15:0] R16_add ;reg[15:0] R_average ;reg[15:0] R_signal ;reg[15:0] R1_signal ;reg[15:0] R2_signal ;reg[15:0] R3_signal ;reg[15:0] R4_signal ;reg[15:0] R5_signal ;reg[15:0] R6_signal ;reg[15:0] R7_signal ;reg[15:0] R8_signal ;reg[15:0] R9_signal ;reg[15:0] R10_signal ;reg[15:0] R11_signal ;reg[15:0] R12_signal ;reg[15:0] R13_signal ;reg[15:0] R14_signal ;reg[15:0] R15_signal ;reg[15:0] R16_signal ;always@(posedgeI_clkornegedgeI_rst_n)begin if(~I_rst_n) begin R_noise <= 16'b0; R1_noise <= 16'b0; R2_noise <= 16'b0; R3_noise <= 16'b0; R4_noise <= 16'b0; R5_noise <= 16'b0; R6_noise <= 16'b0; R7_noise <= 16'b0; R8_noise <= 16'b0; R9_noise <= 16'b0; R10_noise <= 16'b0; R11_noise <= 16'b0; R12_noise <= 16'b0; R13_noise <= 16'b0; R14_noise <= 16'b0; end else begin R_noise <= I_noise ; R1_noise <= R_noise ; R2_noise <= R1_noise ; R3_noise <= R2_noise ; R4_noise <= R3_noise ; R5_noise <= R4_noise ; R6_noise <= R5_noise ; R7_noise <= R6_noise ; R8_noise <= R7_noise ; R9_noise <= R8_noise ; R10_noise <= R9_noise ; R11_noise <= R10_noise; R12_noise <= R11_noise; R13_noise <= R12_noise; R14_noise <= R13_noise; endendalways@(posedgeI_clkornegedgeI_rst_n)begin if(~I_rst_n) begin R_add <= 19'b0; end else begin R_add <= (I_noise+R_noise)+(R1_noise+R2_noise)+(R3_noise+R4_noise)+(R5_noise+R6_noise)+(R7_noise+R8_noise)+(R9_noise+R10_noise)+(R11_noise+R12_noise)+(R13_noise+R14_noise); endendalways@(posedgeI_clkornegedgeI_rst_n)begin if(~I_rst_n) begin R1_add <= 16'b0; R2_add <= 16'b0; R3_add <= 16'b0; R4_add <= 16'b0; R5_add <= 16'b0; R6_add <= 16'b0; R7_add <= 16'b0; R8_add <= 16'b0; R9_add <= 16'b0; R10_add <= 16'b0; R11_add <= 16'b0; R12_add <= 16'b0; R13_add <= 16'b0; R14_add <= 16'b0; R15_add <= 16'b0; R16_add <= 16'b0; end else begin R1_add <= R_add[19:4] ; R2_add <= R1_add ; R3_add <= R2_add ; R4_add <= R3_add ; R5_add <= R4_add ; R6_add <= R5_add ; R7_add <= R6_add ; R8_add <= R7_add ; R9_add <= R8_add ; R10_add <= R9_add ; R11_add <= R10_add ; R12_add <= R11_add ; R13_add <= R12_add ; R14_add <= R13_add ; R15_add <= R14_add ; R16_add <= R15_add ; endendalways@(posedgeI_clkornegedgeI_rst_n)begin if(~I_rst_n) begin R_average <= 16'b0; end else begin if(R_add[18:3]>R16_add) begin R_average <= R_add[18:3]; end else begin R_average <= R16_add; end endendalways@(posedgeI_clkornegedgeI_rst_n)begin if(~I_rst_n) begin R_signal <= 16'b0 ; R1_signal <= 16'b0 ; R2_signal <= 16'b0 ; R3_signal <= 16'b0 ; R4_signal <= 16'b0 ; R5_signal <= 16'b0 ; R6_signal <= 16'b0 ; R7_signal <= 16'b0 ; R8_signal <= 16'b0 ; R9_signal <= 16'b0 ; R10_signal <= 16'b0 ; R11_signal <= 16'b0 ; R12_signal <= 16'b0 ; R13_signal <= 16'b0 ; R14_signal <= 16'b0 ; R15_signal <= 16'b0 ; R16_signal <= 16'b0 ; end else begin R_signal <= I_signal ; R1_signal <= R_signal ; R2_signal <= R1_signal ; R3_signal <= R2_signal ; R4_signal <= R3_signal ; R5_signal <= R4_signal ; R6_signal <= R5_signal ; R7_signal <= R6_signal ; R8_signal <= R7_signal ; R9_signal <= R8_signal ; R10_signal <= R9_signal ; R11_signal <= R10_signal ; R12_signal <= R11_signal ; R13_signal <= R12_signal ; R14_signal <= R13_signal ; R15_signal <= R14_signal ; R16_signal <= R15_signal ; endendalways@(posedgeI_clkornegedgeI_rst_n)begin if(~I_rst_n) begin O_result <= 16'b0 ; end else begin O_result <= R16_signal - R_average; endendEndmodule先利用matlab生成噪声和信号数据，另存为txt文件。编写testbench，对程序进行仿真测试。Testbench程序如下：moduleCFARTest; //Inputs regI_rst_n; regI_clk; reg[15:0]I_noise; reg[15:0]I_signal; //Outputs wire[15:0]O_result; parameterN=30;parameterS=10;reg[15:0]NOISE_L[N-1:0]; reg[15:0]SIGNAL_L[S-1:0]; integerIndex; //InstantiatetheUnitUnderTest(UUT) CFARuut( .I_rst_n(I_rst_n), .I_clk(I_clk), .I_noise(I_noise), .I_signal(I_signal), .O_result(O_result) ); always#5I_clk = ~I_clk; initialbegin //InitializeInputs I_rst_n=0; I_clk=0; I_noise=0; I_signal=0; Index=0; //Wait100nsforglobalresettofinish #100; I_rst_n = 1 ; $readmemh("E:/noise.txt",NOISE_L); $readmemh("E:/signal.txt",SIGNAL_L); end //输入噪声always@(posedgeI_clk) begin if((Index<N)&&(I_rst_n)) begin I_noise<=NOISE_L[Index]; Index<=Index+1; end else begin I_noise<=16'b0; end end ////输入信号always@(posedgeI_clk) begin if((Index<S)&&(I_rst