计算机系统基础：处理器设计

计算机体系结构

处理器设计1

3次课InstructionSetArchitectureAssemblyLanguageViewProcessorstateRegisters,memory,…Instructionsaddl,movl,leal,…HowinstructionsareencodedasbytesLayerofAbstractionAbove:howtoprogrammachineProcessorexecutesinstructionsinasequenceBelow:whatneedstobebuiltUsetrickstomakeitrunfastE.g.,executemultipleinstructionssimultaneouslyCompilerOSCPUDesignCircuitDesignChipLayoutApplicationProgramISA3LogicalDesign&HCLLogicDesignDigitalcircuitWhatisdigitalcircuit?KnowwhataCPUwillbaseonHardwareControlLanguage(HCL)AsimpleandfunctionallanguagetodescribeourCPUimplementationSyntaxlikeCCategoryofCircuitAnalogCircuitUsealltherangeofSignalMostpartisamplifierHardtomodelandautomaticdesignUsetransistorandcapacitanceasbasisWewillnotdiscussithereCategoryofCircuitDigitalCircuitHasonlytwovalues,0and1EasytomodelanddesignUsetruetableandothertoolstoanalyzeUsegateasthebasisThevoltageof1isdifferindifferentkindcircuit.E.g.TTLcircuitusing5voltageas1DigitalSignalsUsevoltagethresholdstoextractdiscretevaluesfromcontinuoussignalSimplestversion:1-bitsignalEitherhighrange(1)orlowrange(0)WithguardrangebetweenthemNotstronglyaffectedbynoiseorlowqualitycircuitelementsCanmakecircuitssimple,small,andfastVoltageTime010OverviewofLogicDesignFundamentalHardwareRequirementsCommunicationHowtogetvaluesfromoneplacetoanotherComputationStorage(Memory)ClockSignalAperiodicsignalClockComputingwithLogicGatesOutputsareBooleanfunctionsofinputsNotanassignmentoperation,justgivethecircuitanameRespondcontinuouslytochangesininputsWithsome,smalldelayVoltageTimeaba&&bRisingDelayFallingDelayaboutaboutaoutout=a&&bout=a||bout=!aAndOrNotCombinationalCircuitsAcyclicNetworkofLogicGatesContinuouslyrespondstochangesoninputsAnysameinputwillgetthesameoutputOutputsbecome(aftersomedelay)BooleanfunctionsofinputsTypicalapplication:ALUAcyclicNetworkInputsOutputsBitEqualityGenerate1ifaandbareequalHardwareControlLanguage(HCL)VerysimplehardwaredescriptionlanguageBooleanoperationshavesyntaxsimilartoClogicaloperationsWe’lluseittodescribecontrollogicforprocessorsBitequalabeqbooleq=(a&&b)||(!a&&!b)HCLExpressionWordEquality32-bitwordsizeHCLrepresentationEqualityoperationGeneratesBooleanvalue=BAeqWord-LevelRepresentationboolEq=(A==B)HCLRepresentationb31Bitequala31eq31b30Bitequala30eq30b1Bitequala1eq1b0Bitequala0eq0eqWordMultiplexorWord-LevelRepresentationsBAOutMUXb31sa31out31b30a30out30b0a0out0HCLRepresentation?WordMultiplexorHCLRepresentationSelectinputwordAorBdependingoncontrolsignalsHCLrepresentationCaseexpressionSeriesoftest:valuepairs(Don’trequiremutually)OutputvalueforfirstsuccessfultestintOut=[s:A;1:B;];defaultcaseHCLWord-LevelExamplesD0D3Out4s0s1MUX4D2D1Selectoneof4inputsbasedontwocontrolbitsHCLcaseexpressionSimplifytestsbyassumingsequentialmatchingintOut4=[!s1&&!s0:D0;!s1:D1;!s0:D2;1:D3;];4-WayMultiplexorHCLRepresentationOFZFSFOFZFSFOFZFSFOFZFSFArithmeticLogicUnitCombinationallogicContinuouslyrespondingtoinputsControlsignalselectsfunctioncomputedCorrespondingto4arithmetic/logicaloperationsinY86AlsocomputesvaluesforconditioncodesWewilluseitasabasiccomponentforourCPUALUYXX+Y0ALUYXX-Y1ALUYXX&Y2ALUYXX^Y3ABABABABSequentialCircuitCombinationalcircuit+memoryandclocksignalHavestateTwosameinputsmaynotgeneratethesameoutputUseclocksignaltocontroltherunofcircuitClockAperiodicsignalthatdetermineswhennewvaluesaretobeloadedintothedevicesTypicalapplication:CPUClockRisingedgefallingedgeStorageClockedRegisterse.g.ProgramCounter(PC),ConditionCodes(CC)HoldsinglewordsorbitsLoadedasclockrisesNot“programregisters”IOClockRegisterOperationStoresdatabitsFormostoftimeactsasbarrierbetweeninputandoutputAsclockrises,loadsinputState=xRisingclockOutput=xInput=yxState=yOutput=yyStateMachineExample0Comb.LogicALU0OutMUX01ClockInLoadStateMachineExample0ClockLoadInOutComb.LogicALU0OutMUX01ClockInLoad?X0X0?1X0StateMachineExample0ClockLoadInOutComb.LogicALU0OutMUX01ClockInLoadX0X0+X00X0X0X0X0StateMachineExample0ClockLoadInOutComb.LogicALU0OutMUX01ClockInLoadX1X0+X10X0X0X0X0X1StateMachineExample0ClockLoadInOutComb.LogicALU0OutMUX01ClockInLoadX1X0+X1+X10X0X0X1X0+X1X0+X1X0+X1StateMachineExample0ClockLoadInOutComb.LogicALU0OutMUX01ClockInLoadX2X0+X1+X20X0X0X1X0+X1X0+X1X0+X1X2StateMachineExample0ClockLoadInOutComb.LogicALU0OutMUX01ClockInLoadX2X0…X2+X20X0X0X1X0+X1X0…X2X0…X2X2X0…X2StateMachineExample0ClockLoadInOutComb.LogicALU0OutMUX01ClockInLoadX3X31X0X0X1X0+X1X0…X2X0…X2X2X0…X2X3StateMachineExample0ClockLoadInOutComb.LogicALU0OutMUX01ClockInLoadX3X31X0X0X1X0+X1X3X3X2X0…X2X3X3StateMachineExample0ClockLoadInOutComb.LogicALU0OutMUX01ClockInLoadX0X0X1AccumulatorcircuitLoadoraccumulateoneachcycleX2X3X4X5X0+X1X0…X2X3X3+X4X3…X5StorageRandom-accessmemoriese.g.RegisterFile,MemoryHoldmultiplewordsAddressinputspecifieswhichwordtoreadorwritePossiblemultiplereadorwriteportsReadwordwhenaddressinputchangesWritewordasclockrisesRegisterFileRegisterfileHoldsvaluesofprogramregisters

%eax,%esp,etc.RegisteridentifierservesasaddressID“F”impliesnoreadorwriteperformedMultiplePortsCanreadand/orwritemultiplewordsinonecycleEachhasseparateaddressanddatainput/outputRegisterfileABWdstWsrcAvalAsrcBvalBvalWReadportsWriteportClockRegisterFileTimingReadingLikecombinationallogicOutputdatageneratedbasedoninputaddress(Aftersomedelay)WritingLikeregisterUpdateonlyasclockrisesRisingclockRegisterfileABsrcAvalAsrcBvalBx2x2y2RegisterfileWdstWvalWClockx2RegisterfileWdstWvalWClocky2MemoryMemoryHoldsprogramdataandinstructionsPortsAsingleaddressinputAdatainputforwriting,andadataoutputforreadingErrorsignalmeansinvalidaddressData

MemoryaddressreadwriteClockdataindataouterror34SequentialCPUImplementation35SEQComponentsCombinationalLogicClockedRegisterMemory36SEQComponentsCombinationalLogicClockedRegisterMemoryALU37SEQComponentsCombinationalLogicClockedRegisterMemoryCombinationalLogicALU38SEQComponentsCombinationalLogicClockedRegisterMemoryCombinationalLogicALURegisterFileMemory39SEQComponentsCombinationalLogicClockedRegisterMemoryRegisterFileMemoryCombinationalLogicALU40SEQComponentsCombinationalLogicClockedRegisterMemoryRegisterFileMemoryCombinationalLogicALUCCPC41SEQComponentsCombinationalLogicClockedRegisterMemoryRegisterFileMemoryCombinationalLogicALUCCPC42SEQComponentsCombinationalLogicClockedRegisterMemoryRegisterFileMemoryCombinationalLogicALUCCPCreadreadwritewrite43SEQComponentsRegisterFileMemoryCombinationalLogicALUCCPCreadreadwritewriteCombinationalLogicALUControllogicMemoryreadsInst.memoryDatamemoryRegisterfile44SEQComponentsRegisterFileMemoryCombinationalLogicALUCCPCreadreadwritewriteSequentialLogicProgramcounter(PC)Conditioncode(CC)RegisterFileMemoriesasingleclocksignal(Allupdatedasclockrises)45ProcessInstructiononSEQTheprocessorneverneedstoreadbackthestateupdatedbyaninstructioninordertocompletetheprocessingofthisinstruction.SEQProcessacompleteinstructionineachcycleAsingleclockcontrolsallstatLoadCCandnewPCWriteregisterfileandmemory460x00c:addl%edx,%ebx#%ebx

0x300CC

0000x00e:jedest#NottakenCycle3:Cycle4:0x006:irmovl$0x200,%edx#%edx

0x200Cycle2:0x000:irmovl$0x100,%ebx#%ebx

0x100Cycle1:ClockCycle1Cycle2Cycle3Cycle4BeginningofCycle347BeginningofCycle3RegisterFile%ebx=0x100%edx=0x200MemoryCombinationalLogicALU1000x00Creadreadwritewritestatesetaccordingto2ndinstructionPC:0x00CCC:100(assume)%edx:0x200%ebx:0x100combinationallogicstartingtoreacttostatechanges0x006:irmovl$0x200,%edx#%edx

0x200Cycle2:480x00c:addl%edx,%ebx#%ebx

0x300CC

0000x00e:jedest#NottakenCycle3:Cycle4:0x006:irmovl$0x200,%edx#%edx

0x200Cycle2:0x000:irmovl$0x100,%ebx#%ebx

0x100Cycle1:ClockCycle1Cycle2Cycle3Cycle4EndofCycle30x00c:addl%edx,%ebx#%ebx

0x300CC

00049EndofCycle3RegisterFile%ebx=0x100%edx=0x200MemoryCombinationalLogicALU1000x00Creadreadwritewritestatesetaccordingto2ndinstructioncombinationallogicgeneratesresultsfor3rdinstructionCycle3:%ebx

0x3000000x00C0x00E500x00c:addl%edx,%ebx#%ebx

0x300CC

0000x00e:jedest#NottakenCycle3:Cycle4:0x006:irmovl$0x200,%edx#%edx

0x200Cycle2:0x000:irmovl$0x100,%ebx#%ebx

0x100Cycle1:ClockCycle1Cycle2Cycle3Cycle4BeginningofCycle451BeginningofCycle4RegisterFile%ebx=0x300%edx=0x200MemoryCombinationalLogicALU0000x00Ereadreadwritewritestatesetaccordingto3rdinstructionPC:0x00ECC:000%edx:0x200%ebx:0x300combinationallogicstartingtoreacttostatechanges0x00e:jedest#NottakenCycle4:520x00c:addl%edx,%ebx#%ebx

0x300CC

0000x00e:jedest#NottakenCycle3:Cycle4:0x006:irmovl$0x200,%edx#%edx

0x200Cycle2:0x000:irmovl$0x100,%ebx#%ebx

0x100Cycle1:ClockCycle1Cycle2Cycle3Cycle4EndofCycle453EndofCycle4RegisterFile%ebx=0x300MemoryCombinationalLogicALU0000x00Ereadreadwritewrite0x00e:jedest#NottakenCycle4:0x00E0x013statesetaccordingto3rdinstructioncombinationallogicgeneratesresultsfor4thinstruction54HowtodesignSEQ?NaïveDesign:One-by-oneStraightforward,butwasteAdvancedDesign:Multi-stagesFormulateinstructionexecutionassequenceofsimplesteps(stages)Like:functionforprogrammingBestuseofhardwareChallenge:usesamegeneralformforallinstructions55Y86InstructionDecodingInstructionFormatInstructionbyte icode:ifunOptionalregisterbyte rA:rBOptionalconstantword valC50rArBDicodeifunrArBvalCOptionalOptional56Byte012345rrmovlrA,rB20rArBirmovlV,rB30FrBVrmmovlrA,D(rB)40rArBDmrmovlD(rB),rA50rArBDOPlrA,rB6fnrArBnop00halt10addl60subl61andl62xorl63Y86InstructionSet57Y86InstructionSetpushlrAA0rAFjXXDest7fnDestpoplrAB0rAFcallDest80Destret90jmp70jle71jl72je73jne74jge75jg76Byte012345rrmovlrA,rB2fnrArBcmovle21cmovl22cmove23cmovne24cmovge25cmovg26example:pushl%edx1:geticode:agetifun:02:getregA:reg[%edx]getregB:reg[F]3:addr:reg[%esp]-44:setmem:reg[%edx]5:setreg:reg[%esp]6:pc:pc+2Lab5:Y86simintnexti(argc,argv){/*getcodeandfunction*/

/*getregisterandimmediate*//*execute*/swith(icode){/*alu+r/wmem+wreg*/pc=next_pc;}}/*doalu*/long_tcompute_alu(op,regA,regB){}/*setmemory*/get_mem_val(m,addr){}/*setmemory*/set_mem_val(m,addr,val){}/*setregs*/set_reg_val(rf,id,val){}12345659InstructionExecutionStagesFetchReadinstructionfrominstructionmemoryDecodeReadprogramregistersExecuteComputevalueoraddressMemoryReadorwritedataWriteBackWriteprogramregistersPCUpdateprogramcounter60InstructionInstructionmemoryPCincrementCCCCALUDatamemoryFetchDecodeExecuteMemoryWritebackRegisterMPCPCAB

RegisterFileEM61SEQHardwareStructureInstructionFlowReadinstructionataddressspecifiedbyPC:1Processthroughstages:2

5Updateprogramcounter:662Executingarith./log.operationFetchRead2bytesDecodeReadoperandregistersExecutePerformoperationSetConditionCcodesMemoryDonothingWritebackUpdateregisterrBPCUpdateIncrementPCby2OPlrA,rB6fnrArBoplrA,rB6fnrArB63StageComputation:arith./log.opsOPlrA,rBicode:ifun

M1[PC]rA:rB

M1[PC+1]

valPPC+2FetchReadinstructionbyteReadregisterbyte

ComputenextPCvalAR[rA]valBR[rB]DecodeReadoperandAReadoperandBvalEvalBifunvalASetCCExecutePerformALUoperationSetconditioncoderegister

Memory

R[rB]valE

WritebackWritebackresult

PCvalPPCupdateUpdatePCvalAR[%edx]=9valBR[%ebx]=21

StageComputation:arith./log.opsOPlrA,rBicode:ifun

M1[PC]rA:rB

M1[PC+1]

valPPC+2FetchvalAR[rA]valBR[rB]DecodevalEvalBifunvalASetCCExecuteMemoryR[rB]valE

WritebackPCvalPPCupdate

subl%edx,%ebx0x00c:6123icode:ifun

M1[0x00C]=6:1rA:rB

M1[0x00C+1]=2:3

valP0x00C+2=0x00EvalE21-9=12ZF0,SF

0,OF0R[%ebx]valE=12

PCvalP=0x00E65InstructionInstructionmemoryPCincrementCCCCALUDatamemoryFetchDecodeExecuteMemoryWritebackicode:ifun,rA:rB

valCRegisterMvalPrA,rBrB,dstMvalA,valBvalA,valBCndvalEaddrs,datavalMPCvalE,valMPCAB

RegisterFileEMvalPCCPCPC66ExecutingrrmovlFetchRead2bytesDecodeReadoperandregisterrAExecuteDonothingMemoryDonothingWritebackUpdateregisterrBPCUpdateIncrementPCby2rrmovlrA,rB20rArB67StageComputation:rrmovlrrmovlrA,rBicode:ifun

M1[PC]rA:rB

M1[PC+1]

valPPC+2FetchReadinstructionbyteReadregisterbyte

ComputenextPCvalAR[rA]DecodeReadoperandAvalE0+valAExecutePerformALUoperation(generalization)

Memory

R[rB]valE

WritebackWritebackresult

PCvalPPCupdateUpdatePC68InstructionInstructionmemoryPCincrementCCCCALUDatamemoryFetchDecodeExecuteMemoryWritebackicode:ifun,rA:rB

valCRegisterMvalPrA,srcBrB,dstMvalA,valBvalA,0CndvalEaddrs,datavalMPCvalE,valMPCAB

RegisterFileEMvalPCCPCPC69ExecutingirmovlFetchRead6bytesDecodeDonothingExecuteDonothingMemoryDonothingWritebackUpdateregisterrBPCUpdateIncrementPCby6irmovlV,rB30FrBV70StageComputation:irmovlirmovlrA,rBicode:ifun

M1[PC]rA:rB

M1[PC+1]valC

M4[PC+2]valPPC+6FetchReadinstructionbyteReadregisterbyteReadconstantvalueComputenextPCDecodevalE0+valCExecutePerformALUoperation(generalization)

MemoryR[rB]valE

WritebackWritebackresult

PCvalPPCupdateUpdatePC71InstructionInstructionmemoryPCincrementCCCCALUDatamemoryFetchDecodeExecuteMemoryWritebackicode:ifun,rA:rB

valCRegisterMvalPsrcA,srcBrB,dstMvalA,valBvalC,0CndvalEaddrs,datavalMPCvalE,valMPCAB

RegisterFileEMvalPCCPCPC72ExecutingrmmovlFetchRead6bytesDecodeReadoperandregistersExecuteComputeeffectiveaddressMemoryWritetomemoryWritebackDonothingPCUpdateIncrementPCby6rmmovlrA,D(rB)40rArBD73StageComputation:rmmovlUseALUforaddresscomputationrmmovlrA,D(rB)icode:ifun

M1[PC]rA:rB

M1[PC+1]valC

M4[PC+2]valPPC+6FetchReadinstructionbyteReadregisterbyteReaddisplacementDComputenextPCvalAR[rA]valBR[rB]DecodeReadoperandAReadoperandBvalEvalB+valCExecuteComputeeffectiveaddress

M4[valE]

valAMemoryWritevaluetomemory

Writeback

PCvalPPCupdateUpdatePC74InstructionInstructionmemoryPCincrementCCCCALUDatamemoryFetchDecodeExecuteMemoryWritebackicode:ifun,rA:rBvalCRegisterMvalPrA,rBdstE,dstMvalA,valBvalC,valBCndvalEvalE,valAvalMPCvalE,valMPCAB

RegisterFileEMvalPCCPCPC75ExecutingmrmovlFetchRead6bytesDecodeReadoperandregisterrBExecuteComputeeffectiveaddressMemoryReadfrommemoryWritebackUpdateregisterrAPCUpdateIncrementPCby6mrmovlD(rB),rA50rArBD76StageComputation:mrmovlUseALUforaddresscomputationmrmovlD(rB),rAicode:ifun

M1[PC]rA:rB

M1[PC+1]valC

M4[PC+2]valPPC+6FetchReadinstructionbyteReadregisterbyteReaddisplacementDComputenextPCvalBR[rB]DecodeReadoperandBvalEvalB+valCExecuteComputeeffectiveaddress

valM

M4[valE]MemoryReaddatafrommemory

R[rA]

valMWritebackUpdateregisterrAPCvalPPCupdateUpdatePC77InstructionInstructionmemoryPCincrementCCCCALUDatamemoryFetchDecodeExecuteMemoryWritebackicode:ifun,rA:rB

valCRegisterMvalPsrcA,rBdstE,rAvalA,valBvalC,valBCndvalEvalE,datavalMPCvalE,valMPCAB

RegisterFileEMvalPCCPCPC78ExecutingpushlFetchRead2bytesDecodeReadstackpointerandregisterrAExecuteDecrementstackpointerby4MemoryStorevalAattheaddressofnewstackpointerWritebackUpdatestackpointerPCUpdateIncrementPCby2pushlrAa0rAF79StageComputation:pushlUseALUtodecrementstackpointerpushlrAicode:ifun

M1[PC]rA:rB

M1[PC+1]

valPPC+2FetchReadinstructionbyteReadregisterbyte

ComputenextPCvalAR[rA]valBR[%esp]DecodeReadvalAReadstackpointervalEvalB+(-4)ExecuteDecrementstackpointerM4[valE]

valAMemoryStoretostackR[%esp]valEWritebackUpdatestackpointerPCvalPPCupdateUpdatePC80InstructionInstructionmemoryPCincrementCCCCALUDatamemoryFetchDecodeExecuteMemoryWritebackicode:ifun,rA:rB

valCRegisterMvalPrA,%esp%esp,dstMvalA,valB-4,valBCndvalEvalE,valAvalMPCvalE,valMPCAB

RegisterFileEMvalPCC81ExecutingpoplFetchRead2bytesDecodeReadstackpointerExecuteIncrementstackpointerby4MemoryReadfromoldstackpointerWritebackUpdatestackpointerUpdateregisterrAPCUpdateIncrementPCby2poplrAb0rAF82StageComputation:poplpoplrAicode:ifun

M1[PC]rA:rB

M1[PC+1]

valPPC+2FetchReadinstructionbyteReadregisterbyte

ComputenextPCvalAR[%esp]valBR[%esp]DecodeReadstackpointerReadstackpointervalEvalB+4ExecuteIncrementstackpointervalM

M4[valA]MemoryReadfromstackR[%esp]valER[rA]

valMWritebackUpdatestackpointerWritebackresultPCvalPPCupdateUpdatePCUseALUtoincrementstackpointerupdatetworegisters(special:rA=%esp)83InstructionInstructionmemoryPCincrementCCCCALUDatamemoryFetchDecodeExecuteMemoryWritebackicode:ifun,rA:rB

valCRegisterMvalP%esp,%esp%esp,rAvalA,valB+4,valBCndvalEvalA,datavalMPCvalE,valMPCAB

RegisterFileEMvalPCCPCPC84ExecutingJumpsjXXDest7fnDestXXXXfallthru:XXXXtarget:NottakenTaken85ExecutingJumpsFetchRead5bytesIncrementPCby5DecodeDonothingExecuteDeterminewhethertotakebranchbasedonjumpconditionandconditioncodesMemoryDonothingWritebackDonothingPCUpdateSetPCtoDestifbranchtakenortoincrementedPCifnotbranch86StageComputation:JumpsjXXDesticode:ifun

M1[PC]valC

M4[PC+1]valPPC+5FetchReadinstructionbyteReaddestinationaddressFallthroughaddressDecodeCnd

Cond(CC,ifun)ExecuteTakebranch?

Memory

Writeback

PCCnd?valC:valPPCupdateUpdatePCComputebothaddressesChosebasedonCCandifun87InstructionInstructionmemoryPCincrementCCCCALUDatamemoryFetchDecodeExecuteMemoryWritebackicode:ifun,rA:rB

valCRegisterMvalPsrcA,srcBdstE,dstMvalA,valBaluA,aluBCndvalEaddrs,datavalMPCvalE,valMPCAB

RegisterFileEMCCvalP,valCPCPC88ExecutingcallcallDest80DestXXXXreturn:XXXXtarget:89ExecutingcallFetchRead5bytesIncrementPCby5DecodeReadstackpointerExecuteDecrementstackpointerby4MemoryWriteincrementedPCtonewvalueofstackpointerWritebackUpdatestackpointerPCUpdateSetPCtoDest90StageComputation:callcallDesticode:ifun

M1[PC]

valC

M4[PC+1]valPPC+5FetchReadinstructionbyteReaddestinationaddressComputereturnpointvalBR[%esp]DecodeReadstackpointervalEvalB+–4ExecuteDecrementstackpointerM4[valE]

valPMemoryWritereturnvalueonstackR[%esp]valE

WritebackUpdatestackpointer

PCvalCPCupdateSetPCtodestinationUseALUtodecrementstackpointer91InstructionInstructionmemoryPCincrementCCCCALUDatamemoryFetchDecodeExecuteMemoryWritebackicode:ifun,rA:rB

valCRegisterMvalPsrcA,%esp%esp,dstMvalA,valB-4,valBCndvalEvalE,valPvalMPCvalE,valMPCAB

RegisterFileEMvalCCCPCPC92Executingretret90XXXXreturn:93ExecutingretFetchRead1byteDecodeReadstackpointerExecuteIncrementstackpointerby4MemoryReadreturnaddressfromoldstackpointerWritebackUpdatestackpointerPCUpdateSetPCtoreturnaddress94StageComputation:retreticode:ifun

M1[PC]

FetchReadinstructionbyte

valAR[%esp]valBR[%esp]DecodeReadoperandstackpointerReadoperandstackpointervalEvalB+4ExecuteIncrementstackpointervalM

M4[valA]MemoryReadreturnaddressR[%esp]valE

WritebackUpdatestackpointer

PCvalMPCupdateSetPCtoreturnaddressUseALUtoincrementstackpointer95InstructionInstructionmemoryPCincrementCCCCALUDatamemoryFetchDecodeExecuteMemoryWritebackicode:ifun,rA:rB

valCRegisterMvalP%esp,%esp%esp,dstMvalA,valB4,valBCndvalEvalA,datavalMPCvalE,valMPCAB

RegisterFileEMvalMCCPCPC96ExecutingcmovXXFetchRead2bytesDecodeReadoperandregisterrAExecuteDeterminewhethertomoveMemoryDonothingWritebackUpdateregisterrB

ifmovetakenPCUpdateIncrementPCby2cmovXXrA,rB2fnrArB97StageComputation:cmovXXcmovXXrA,rBicode:ifun

M1[PC]rA:rB

M1[PC+1]

valPPC+2FetchReadinstructionbyteReadregisterbyte

ComputenextPCvalAR[rA]DecodeReadoperandAvalE0+valACnd

Cond(CC,ifun)ExecutePerformALUoperationTakemove?

Memory

Cnd?R[rB]valE:-

WritebackWritebackresultifmovetaken

PCvalPPCupdateUpdatePC98InstructionInstructionmemoryPCincrementCCCCALUDatamemoryFetchDecodeExecuteMemoryWritebackicode:ifun,rA:rB

valCRegisterMvalPrA,srcBrB,dstMvalA,valBvalA,0CndvalEaddrs,datavalMPCvalE,valMPCAB

RegisterFileEMvalPCCPCPC99ComputationStepsAllinstructionsfollowsamegeneralpatternDifferinwhatgetscomputedoneachstepReadinstructionbyteReadregisterbyteReadconstantwordComputenextPCReadoperandAReadoperandBPerformALUoperationSetconditioncodereg.Read/WriteMemoryWritebackALUresultWritebackMemoryresultUpdatePCOPl

rA,rBicode:ifun

M1[PC]rA:rB

M1[PC+1]

valPPC+2FetchvalAR[rA]valBR[rB]DecodevalEvalBOPvalASetCCExecuteMemoryR[rB]valE

WriteBackPCvalPPCupdateicode,ifunrA,rBvalCvalPvalA,srcAvalB,srcBvalECondcodevalMdstEdstMPC

100ComputationStepsAllinstructionsfollowsamegeneralpatternDifferinwhatgetscomputedoneachstepOPl

rA,rBicode:ifun

M1[PC]rA:rB

M1[PC+1]

valPPC+2FetchvalAR[rA]valBR[rB]DecodevalEvalBOPvalASetCCExecuteMemoryR[rB]valE

WriteBackPCvalPPCupdateicode,ifunrA,rBvalCvalPvalA,srcAvalB,srcBvalECondcodevalMdstEdstMPCcallDesticode:ifun

M1[PC]valC

M4[PC+1]valPPC+5valBR[%esp]valEvalB+–4M4[valE]

valPR[%esp]valE

PCvalC

101InstructionInstructionmemoryPCincrementCCCCALUDatamemoryFetchDecodeExecuteMemoryWritebackicode:ifun,rA:rBvalCRegisterMvalPsrcA,srcBdstE,dstMvalA,valBaluA,aluBCndvalEaddrs,datavalMPCvalE,valMPCAB

RegisterFileEMCCnewPCPCPC102DeterminateValuesFetchPC ProgramCounticode Instr.Codeifun Instr.FunctionrA Instr.RegisterArB Instr.RegisterBvalC Instr.ConstantvalP IncrementedPCDecodevalA RegistervalueAvalB RegistervalueBExecutevalE ALUresultCC

ConditionCodeCnd ConditionFlagMemory valM ValuefromMemoryWritebackvalE

ALUresultvalM

ValuefromMemory103IndeterminateValuesDecodesrcA locationofvalA

rA,%espsrcB locationofvalB

rB,%espExecutealuA inputAofALU

valA,valC,+4,-4aluB inputBofALU

valB,0Memoryaddr addressofmemory

valA,valEdata dataofMemory

valA,valPWritebackdstE dest.ofALUresult

rB,%espdstM destofMemory

rAPCnewPC nextofPC

valP,valC,valM104InstructionInstructionmemoryPCincrementCCCCALUDatamemoryFetchDecodeExecuteMemoryWritebackicode:ifun,rA:rBvalCRegisterMvalPsrcA,srcBdstE,dstMvalA,valBaluA,aluBCndvalEaddrs,datavalMPCvalE,valMnewPCPCAB

RegisterFileEMPCPCCC105106InstructionMemoryrBicodeifunrAPCPCincrementvalCvalPdstEdstMRegisterfileABMEdstEdstMvalBvalACCALUDatamemoryALUAALUBAddrreadwriteALUfundataoutCndDatavalEvalMNewPCnewPCsrcAsrcBsrcAsrcBDecodeExecuteMemoryPCFetchWriteBackMemControl107DifferencebetweensemanticsandimplementationISAEverystagemayupdatesomestates,theseupdatesoccursequentiallySEQAllthestateupdateoperationsoccursimultaneouslyatclockrisingpopl%espneedtowritesameregistertwice.Sotheregisterfilecontrollogicmustprocessit.108SEQHardwareBlueboxes: