数字集成电路：反相器

数字集成电路

-电路、系统与设计反相器计算VIHandVIL反相器增益VDD产生的增益VTC模拟器件参数变化的影响00.511.522.500.511.522.5Vin(V)Vout(V)GoodPMOSBadNMOSGoodNMOSBadPMOSNominal传播延时CMOS反相器传播延时

1阶分析CMOS反相器传播延时

2阶分析CMOS反相器多晶硅InOut金属1VDDGNDPMOSNMOS1.2mm=2l瞬态响应tp=0.69CL(Reqn+Reqp)/2?tpLHtpHL功能设计保持小电容增加晶体管尺寸注意self-loading!增加VDD(????)VDD对延时的影响注意：这一公式只在器件速度饱和时成立，因此在低电源电压会有偏差。器件尺寸NMOS/PMOS尺寸系数b=Wp/Wn上升时间对延时的影响反相器尺寸反相器链CLIfCLisgiven:Howmanystagesareneededtominimizethedelay?Howtosizetheinverters?Mayneedsomeadditionalconstraints.InOut反响器延时

Minimumlengthdevices,L=0.25mmAssumethatforWP=2WN=2Wsamepull-upandpull-downcurrentsapprox.equalresistancesRN=RPapprox.equalrisetpLHandfalltpHLdelaysAnalyzeasanRCnetworktpHL=(ln2)RNCLtpLH=(ln2)RPCLDelay(D):2WWLoadforthenextstage:带负载的反相器Load(CL)DelayAssumptions:noload->zerodelayCLtp=k

RWCLRWRWWunit=1kisaconstant,equalto0.69带负载的反相器LoadDelayCintCLDelay=kRW(Cint+CL)=kRWCint+kRWCL

=kRW

Cint(1+CL/Cint)=Delay(Internal)+Delay(Load)CN=CunitCP=2Cunit2WW延时公式Cint=gCgin

with

g

1f=CL/Cgin

-effectivefanoutR=Runit/W;Cint=WCunittp0=0.69RunitCunit反相器链的应用CLInOut12Ntp=tp1+tp2+…+tpN最佳给定尖端N值DelayequationhasN-1unknowns,Cgin,2–Cgin,NMinimizethedelay,findN-1partialderivativesResult:Cgin,j+1/Cgin,j=Cgin,j/Cgin,j-1Sizeofeachstageisthegeometricmeanoftwoneighborseachstagehasthesameeffectivefanout(Cout/Cin)eachstagehasthesamedelay最佳延时Wheneachstageissizedbyfandhassameeff.fanout

f:MinimumpathdelayEffectivefanoutofeachstage:例CL=8C1InOutC11ff2CL/C1hastobeevenlydistributedacrossN=3stages:最佳阶段数量Foragivenload,CLandgiveninputcapacitanceCinFindoptimalsizingfForg=0,f=e,N=lnF最佳有效扇出fOptimumfforgivenprocessdefinedbygfopt=3.6for

g=1自载对tp的影响NoSelf-Loading,g=0WithSelf-Loadingg=1不同驱动器结构与F的关系缓冲器设计111186464646442.881622.6N f tp1 64 652 8 183 4 154 2.8 15.3功耗CMOS的功耗产生来源?动态功耗Energy/transition=CL*Vdd2Power=Energy/transition*f=CL*Vdd2

*f减小CL,Vdd,和f

来降低能量.VinVoutCLVdd与晶体管尺寸无关为减小摆幅而进行的电路修正绝热装置222AdiabaticCharging节点转换和功耗最小能量的晶体管尺寸Goal:MinimizeEnergyofwholecircuitDesignparameters:fandVDDtp

tprefofcircuitwithf=1andVDD=Vref晶体管尺寸(2)PerformanceConstraint(g=1)EnergyforsingleTransition晶体管尺寸(3)短路电流怎么保持较低短路电流？Shortcircuitcurrentgoestozeroiftfall>>trise,butcan’tdothisforcascadelogic,so...最小化短路电流功耗Vdd=1.5Vdd=2.5Vdd=3.3泄漏电流反偏漏二极管JS=10-100pA/mm2at25degCfor0.25mmCMOSJSdoublesforevery9degC!SubthresholdLeakageComponent静态功耗Wastedenergy…Shouldbeavoidedinalmostallcases,butcouldhelpreducingenergyinothers(e.g.senseamps)减小功耗的方法首要选择:减小电压!RecentyearshaveseenanaccelerationinsupplyvoltagereductionDesignatverylowvoltagesstillopenquestion(0.6…0.9Vby2010!)减小开关电流减小物理电容DeviceSizing:forF=20fopt(energy)=3.53,fopt(performance)=4.47工艺尺寸

缩小的影响工艺尺寸缩小的目的更为廉价:用同样一个片所需的钱卖出更多的晶体管把同样的产品做得更便宜晶体管的价格降低更快、更小、低功耗工艺尺寸缩小Goalsofscalingthedimensionsby30%:Reducegatedelayby30%(increaseoperatingfrequencyby43%)DoubletransistordensityReduceenergypertransitionby65%(50%powersavings@43%increaseinfrequencyDiesizeusedtoincreaseby14%pergenerationTechnologygenerationspans2-3yearsTechnologyGenerations技术革命(2000data)InternationalTechnologyRoadmapforSemiconductors18617717116013010690MaxmPpower[W]1.41.26-71.5-1.818019991.71.6-1.46-71.5-1.8200014.9-3.611-37.1-2.53.5-22.1-1.6Maxfrequency[GHz],Local-Global2.52.32.12.42.0Bat.power[W]109-10987Wiringlevels0.3-0.60.5-0.60.6-0.90.9-1.21.2-1.5Supply[V]30406090130Technologynode[nm]20142011200820042001YearofIntroductionNodeyears:2007/65nm,2010/45nm,2013/33nm,2016/23nm技术革命(1999)ITRS工艺尺寸路标

继续加速工艺尺寸缩小(1)MinimumFeatureSize

工艺尺寸缩小(2)Numberofcomponentsperchip

工艺尺寸缩小(3)PropagationDelay

tp

decreasesby13%/year50%every5years!工艺尺寸缩小(4)FromKuroda工艺尺寸缩小模型

长沟器件的尺寸缩小情况

晶体管缩小比例mProcessorScalingP.Gelsinger:mProcessorsfortheNewMillenium,ISSCC2001mProcessorPowerP.Gelsinger:mProcessorsfortheNewMillenium,ISSCC2001mProcessorPerformanceP.Gelsinger:mProcessorsfortheNewMillenium,ISSCC20012010展望Performance2X/16months1TIP(terrainstructions/s)30GHzclockSizeNooftransistors:2BillionDi