超大规模集成电路第六次作业2016秋-段成华

ThefollowingfigureshowsaC2MOSbaseddual-edgetriggeredregister.Itsadvantageisthatalowerfrequencyclock(halfoftheoriginalrate)isdistributedforthesamefunctionalthroughput,resultinginpowersavingsintheclockdistributionnetwork.CalculatethetimingparametersofsetuptimetSU,holdtimetHandpropagationdelaytCOoftheregisterwithrespecttotherisingedgeoftheclockCLK,giventhattheinverterdelayistINV.AssumethatthetransistorsarewiththeminimumsizeandC=20fF.Verifythefunctionofthedual-edgetriggeredregisteranditstimingparametersin(1)byusingHSPICEandTSMC0.18umCMOStechnologymodelwith1.8Vpowersupply.DeterminerespectivelythemaximumworkfrequencyfmaxoftheregisterbyHSPICEsimulation.Determinethemaximumfreshcycleoftheregister.Solution:、C2MOS电路对时钟重叠不敏感所以CLK和CLK’因反相器导致的延时问题不予考虑。CLK在上升沿之前为低电平，假设输入D为1，M9，M10和M1导通，则Y为0，所以tSU=tINV（类似反相器的传播延时）+tINV（CLK到CLK’反相器导致的延时）=2tINV；由于上升沿到来后CLK为高电平，M9和M10关断，所以在时钟变为高电平后输入的任何变化都不会影响输出，所以tH=0；当CLK上升沿到来，则M14，M13和M12导通Y=0反向输出到Q（为1），所以tCO=tINV（类似反相器的传播延时）+tINV（CLK到CLK’反相器导致的延时）=2tINV。可以看出C2MOS电路相比于静态电路延时很小。、代码如下：.titleC2MOSLOGICOFINVERTERS.lib'C:\synopsys\Hspice_D-2010.03-SP1\tsmc018\mm018.l'TT*set0.18umlibrary.optionspost=2list.temp27.globalvddVddvddgnd1.8vclknvclkn00.9pulse0.01.81500p5p5p2990p6000pvinvin00.9PWL0p0,1280p0,1285p1.8C1voutxgnd20fC2voutygnd20fC3vqgnd20f.subcktPN-TYPE-INV1clknclkpDoutn2n1wn=0.35uwp=1.0ut=0.5um1n2DgndgndNCHl=0.2uw=wnad='wn*t'pd='wn+2*t'as='wn*t'ps='wn+2*t'm2outclknn2gndNCHl=0.2uw=wnad='wn*t'pd='wn+2*t'as='wn*t'ps='wn+2*t'm3outclkpn1vddPCHl=0.2uw=wpad='wp*t'pd='wp+2*t'as='wp*t'ps='wp+2*t'm4n1DvddvddPCHl=0.2uw=wpad='wp*t'pd='wp+2*t'as='wp*t'ps='wp+2*t'.ends.subcktPN-TYPE-INV2clknclkpDoutwn=0.35uwp=1.0ut=0.5um1n2DgndgndNCHl=0.2uw=wnad='wn*t'pd='wn+2*t'as='wn*t'ps='wn+2*t'm2outclknn2gndNCHl=0.2uw=wnad='wn*t'pd='wn+2*t'as='wn*t'ps='wn+2*t'm3outclkpn1vddPCHl=0.2uw=wpad='wp*t'pd='wp+2*t'as='wp*t'ps='wp+2*t'm4n1DvddvddPCHl=0.2uw=wpad='wp*t'pd='wp+2*t'as='wp*t'ps='wp+2*t'.ends.subcktPN-TYPE-tINVclkpclknoutn2n1wn=0.35uwp=1.0ut=0.5um1outclkpn2gndNCHl=0.2uw=wnad='wn*t'pd='wn+2*t'as='wn*t'ps='wn+2*t'm2outclknn1vddPCHl=0.2uw=wpad='wp*t'pd='wp+2*t'as='wp*t'ps='wp+2*t'.ends.subcktinvinoutwn=0.35uwp=1.0ut=0.5um1outingndgndNCHl=0.2uw=wnad='wn*t'pd='wn+2*t'as='wn*t'ps='wn+2*t'm2outinvddvddPCHl=0.2uw=wpad='wp*t'pd='wp+2*t'as='wp*t'ps='wp+2*t'.endsX1vclknvclkpinvX2vclknvclkpvinvoutxn2n1PN-TYPE-INV1X3vclkpvclknvoutxvqPN-TYPE-INV2X4vclkpvclknvoutyn2n1PN-TYPE-tINVX5vclknvclkpvoutyvqPN-TYPE-INV2.op.tran5p18000p.meastranvqmaxmaxv(vq)from=50pto=18000p.meastranvqminminv(vq)from=50pto=18000p.meastrantplh_Tco+trigv(vclkn)+val=0.9+rise=1+targv(vq)+val='0.5*(vqmax-vqmin)+vqmin'+rise=1.printdcv(vclkn)v(vin)v(voutx)v(vouty)v(vq).end周期为6000ps，设置建立时间为220ps则得到如下测量数据和图形：周期为6000ps，设置建立时间为215ps则得到如下测量数据和图形：对比以上两图当tSU两=215ps时候电压只达到了0.84V，而220ps时候达到了1.2364V，所以建立时间近似为220ps。而对比于一个反相器带载为20fF的延时约为110ps，所以预测的建立时间近似正确。为了为了使得测量的tCO更准确，将建立时间给的足够设为500ps，得到测量数据和图形如下：分析如下：得到的延时时间为284ps，也约为一个反相器延时的二倍，延时偏大的原因可能和中间一级的负载电容有关。根据上图可以知道当上升沿到来则直接将输入信号变为0，发现输出vp正常，所以不需要保持时间即tH=0.、周期为500ps，CLK高电平期间作为输入vin的建立时间，切出入vin恰好为上升沿开始位置，这样可以使整个高电平作为建立时间tSU，正常来说周期为440ps是可以的，实测到周期为500ps时候，下降沿触发传递到vq，到低电平结束vq最大为1V，所以周期不可能再小了，再小整个建立时间不够，D是无法传输到X处的，同时传递时间也不够，整个触发器处于无法正常工作的状态