第5章 时序状态机设计

第5章时序状态机设计第5章时序状态机设计21有限状态机状态机设计实例5.1有限状态机

有限状态机及其设计技术是数字系统设计中的重要组成部分，是实现高效率、高可靠和高速控制逻辑系统的重要途径。有限状态机FSM（FiniteStateMachine），其在任意时刻都处于有限状态集合中的某一种状态。有限状态机是指输出取决于过去输出部分和当前输入部分的时序逻辑电路。有限状态机又可以认为是组合逻辑和寄存器逻辑的一种组合。状态机特别适合描述那些发生有先后顺序或者有逻辑规律的事件，其实这就是状态机的本质。状态机就是对具有逻辑顺序或时序规律的事件进行描述的一种方法。5.2状态机设计实例1．穆尔型状态机设计实例“1101”序列检测器【例5.2-1】

穆尔型状态机的VerilogHDL三always块描述实例。modulemoore(inputclk,inputrst,inputdin,outputregdout);5.2状态机设计实例parameters0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100;//状态说明reg[2:0]present_state,next_state; //现态、次态//状态模块always@(posedgeclkorposedgerst)beginif(rst)present_state=s0;elsepresent_state=next_state;end//次态always@(*)begincase(present_state)s0:if(din==1)next_state<=s1;elsenext_state<=s0;s1:if(din==1)next_state<=s2;elsenext_state<=s0;5.2状态机设计实例s2:if(din==0)next_state<=s3;elsenext_state<=s2;s3:if(din==1)next_state<=s4;elsenext_state<=s0;s4:if(din==0)next_state<=s0;elsenext_state<=s2;default:next_state<=s0;endcaseendalways@(*)beginif(present_state==s4)dout<=1;elsedout<=0;endendmodule5.2状态机设计实例【例5.2-2】穆尔型状态机的Testbench仿真测试。5.2状态机设计实例2．米利型状态机设计实例“1101”序列检测器【例5.2-3】米利型状态机的VerilogHDL三always块描述实例。modulemealy(inputclk,inputrst,inputdin,outputregdout);5.2状态机设计实例parameters0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;reg[1:0]present_state,next_state;//状态模块always@(posedgeclkorposedgerst)beginif(rst)present_state=s0;elsepresent_state=next_state;end//次态模块always@(*)begincase(present_state)s0:if(din==1)next_state<=s1;elsenext_state<=s0;s1:if(din==1)next_state<=s2;elsenext_state<=s0;5.2状态机设计实例s2:if(din==0)next_state<=s3;elsenext_state<=s2;s3:if(din==1)next_state<=s1;elsenext_state<=s0;default:next_state<=s0;endcaseend//输出模块always@(*)beginif((present_state==s3)&&(din==1))dout<=1;elsedout<=0;endendmodule5.2状态机设计实例【例5.2-4】米利型状态机的VerilogHDL双always块描述实例。modulemealy(inputclk,inputrst,inputdin,outputregdout);parameters0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;reg[1:0]present_state,next_state;//状态模块always@(posedgeclkorposedgerst)beginif(rst)present_state=s0;elsepresent_state=next_state;end5.2状态机设计实例//次态和输出模块always@(*)begindout<=0;case(present_state)s0:if(din==1)next_state<=s1;elsenext_state<=s0;s1:if(din==1)next_state<=s2;elsenext_state<=s0;s2:if(din==0)next_state<=s3;elsenext_state<=s2;s3:if(din==1)beginnext_state<=s1;dout<=1;endelsenext_state<=s0;default:next_state<=s0;endcaseendendmodule5.2状态机设计实例【例5.2-5】米利型状态机的VerilogHDL单always块描述实例。modulemealy(inputclk,inputrst,inputdin,outputregdout);parameters0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;reg[1:0]state;//状态模块always@(posedgeclkorposedgerst)beginif(rst)beginstate=s0;dout<=0;end5.2状态机设计实例elsebegindout<=0;case(state)s0:if(din==1)state<=s1;elsestate<=s0;s1:if(din==1)state<=s2;elsestate<=s0;s2:if(din==0)state<=s3;elsestate<=s2;s3:if(din==1)beginstate<=s1;dout<=1;endelsestate<=s0;default:state<=s0;endcaseendendendmodule5.2状态机设计实例米利型状态机的Testbench仿真测试米利型状态机仿真：单always块描述5.2状态机设计实例【例5.2-6】状态机描述实例，A是输入，X是穆尔型输出，Y是米利型输出。modulemealy_moore( inputclk, inputrst_n, inputa, outputregx,y ); parameters0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;

reg[1:0]present_state,next_state; //状态模块 always@(posedgeclkornegedgerst_n)begin if(!rst_n)present_state<=s0;//在rst_n下降沿设s0为初态 elsepresent_state<=next_state; end

5.2状态机设计实例//第二个always是将present_state和输入a作为敏感变量 always@(present_stateora)begin

case(present_state)

s0:begin

x<=0;y<=0;

next_state<=(a==1)?s2:s0; end s1:begin

x<=1;

if(a==0)begin

y<=1;next_state<=s0;

end elsebegin

y<=0;

next_state<=s1;

end

end5.2状态机设计实例 s2:begin

x<=0;

if(a==0)begin

y<=1;

next_state<=s0;

end elsebegin

y<=0;

next_state<=s3;

end

end s3:begin

x<