交通灯实验报告-4

-9--1-EDA实验报告交通灯设计姓名：张惠洋班级：020915学号：02091463

EDA实验报告—交通灯的控制一实验要求：分两个方向（1、2），每个方向各有红（R）、绿（G）、黄（Y）三个交通灯。有自动、手动两种控制方式。在自动方式下，控制器的状态转移表为：状态 亮灯 停留时间S0 R1,G2 2秒S1 R1,Y2 1秒S2 G1,R2 2秒S3 Y1,R2 1秒在手动方式下，按下按钮K0~K3时直接进入对应序号的状态，随后即转入自动方式。交通灯、按钮分别利用实验板上的发光二极管、按钮。二实验器材： PC机一台、FPGA教学实验板一块三实验原理与内容：1原理 (1)本题中交通灯的状态可用有限状态机模型描述。根据输出与输入之间的关系，有限状态机可以分为两种类型：Moore和Mealy型。这两种状态机的区别在于：Mealy型状态机的输出由状态机的输入和状态机的状态共同决定；Moore型状态机的输出仅与状态机的状态有关，而与状态机的输入无关。本题中的输出由六个发光二级光显示，其状态仅与当前状态机的状态有关，故该题为Moore模型的状态机。下图为状态机的状态表：状态表当前状态下一状态输出K0=0K1=0K2=0K3=0时间未到时间到S0S0S1S2S3S0S1011101S1S0S1S2S3S1S2011110S2S0S1S2S3S2S3101011S3S0S1S2S3S3S0110011状态转移图：S0/011101S2/101011S3/110011S1/011110K3=0/时间未到 K3=0/时间未到S0/011101S2/101011S3/110011S1/011110 K0=0K1=0/时间到 K0=0 K3=0 K0=0/时间到 K2=0/时间到 K3=0 K1=0K3=0/时间未到 k1=0 k2=0/时间未到 K2=0K3=0/时间到K2=0(2)本题中所用到的FPGA芯片为CYCLONEEP1C6Q240C8，时钟为4M。故用到一个4M的时钟分频器。2.程序设计组件一：实体jiaotongdeng的程序libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityjiaotongdengisport( clk:instd_logic; k0 :instd_logic; k1 :instd_logic; k2 :instd_logic; k3 :instd_logic; r1,g1,y1,r2,g2,y2 :outstd_logic );endjiaotongdeng;architecturebehaviorofjiaotongdengis typestate_typeis(s0,s1,s2,s3);——用枚举类型进行状态定义 signalcurrent_state,next_state:state_type;——状态信号的定义 signalcounter:std_logic_vector(6downto0);begin synch:process——同步单元 begin waituntilclk'eventandclk='1'; counter<=counter; ifcounter<5then counter<=counter+1; else counter<=(others=>'0'); endif; endprocess; process begin waituntilclk'eventandclk='1'; current_state<=next_state; endprocess; state_trans:process(current_state,k0,k1,k2,k3) ——描述每种状态下电路表现 begin casecurrent_stateis whens0=> ifk0='0'then next_state<=s0; else ifk1='0'then next_state<=s1; else ifk2='0'then next_state<=s2; else ifk3='0'then next_state<=s3; else ifcounter<1then next_state<=s0; else next_state<=s1; endif; endif; endif; endif; endif; whens1=> ifk0='0'then next_state<=s0; else ifk1='0'then next_state<=s1; else ifk2='0'then next_state<=s2; else ifk3='0'then next_state<=s3; else ifcounter<2then next_state<=s1; else next_state<=s2; endif; endif; endif; endif; endif; whens2=> ifk0='0'then next_state<=s0; else ifk1='0'then next_state<=s1; else ifk2='0'then next_state<=s2; else ifk3='0'then next_state<=s3; else ifcounter<4then next_state<=s2; else next_state<=s3; endif; endif; endif; endif; endif; whens3=> ifk0='0'then next_state<=s0; else ifk1='0'then next_state<=s1; else ifk2='0'then next_state<=s2; else ifk3='0'then next_state<=s3; else ifcounter<5then next_state<=s3; else next_state<=s0; endif; endif; endif; endif; endif; endcase; endprocess;ouput:process(current_state) begin——显示程序 casecurrent_stateis whens0=> r1<='0'; g1<='1'; y1<='1'; r2<='1'; g2<='0'; y2<='1'; whens1=> r1<='0'; g1<='1'; y1<='1'; r2<='1'; g2<='1'; y2<='0'; whens2=> r1<='1'; g1<='0'; y1<='1'; r2<='0'; g2<='1'; y2<='1'; whens3=> r1<='1'; g1<='1'; y1<='0'; r2<='0'; g2<='1'; y2<='1'; endcase; endprocess; endbehavior;组件二：分频器实体devide的程序libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitydevideisport(clk:instd_logic;clk_out:outstd_logic);enddevide;architecturearc_devideofdevideissignalcount:std_logic_vector(21downto0);begin process begin waituntilclk'eventandclk='1'; if(count<3999999)then count<=count+1; clk_out<='0'; else count<=(others=>'0'); clk_out<='1'; endif; endprocess; endarchitecturearc_devide;3.实验连接图如上图所示，该交通灯控制系统由两个实体组成。实体clk为4M的时钟分频器，clk是输入口，接的是FPGA产生的时钟信号，clk_out是输出口，输出分频后的时钟脉冲。主实体jiaotongdeng则实现状态机的状态转换逻辑控制。其k0~k3口是输入口，为手动方式的控制按钮，r1,r2,g1,g2,y1,y2为六个输出，控制六个发光二极管的亮灭。六个发光二级管的亮灭代表六个状态机的状态，从而实现交通灯控制的功能。4.时序波形分析（k0,k1,k2,k3=0）上图为4个状态进行转换的时序波形。可见（r1,g1,y1,r2,g2,y2）的状态转换符合011101》011110》101011》110011》011101》……的顺序循环。（k0=0）上图为k0=0时的输出状态s0，输出恒为011101。即亮灯为R1，G2。保持时间2S。