EDA实验报告序列发生器

EDA试验报告试验目的：设计一个含数码管显示的七位二进制序列发生器。试验内容：原理说明：多位数码显示电路由显示字符的段选线和选通数码管的位选线把握。各位数码管共用8方式，利用人眼视觉暂留效应及数码管余辉特性，可以“同时”显示出多位数码管的字符。工程构造框架：序列发生器7SEG译码器abcdefg七段试验流程：设计序列发生器7SEG译码器完成顶层电路图连接完成仿真，下载测试试验具体步骤：1、设计序列发生器序列发生器是产生一组0、1二进制码按特定挨次排列的串行信号的仪器。利用移位存放器设计一个七位二进制序列发生器。创立工程文件：单击界面左上角的file，执行file--->NewProjectWizard 命令，翻开工程导向，在第一页中分别输入建工程所在路径，工程名称和顶层实体名称〔同名〕器件选择：FamilyFLEX10K，TargetdeviceSpecial...Availabledevice中选择EPF10K20TI144-4。需要说明的是，目标器件在创立工程时已经选择完毕，如Assignments->DeviceDevice设置对话框修改DevicefamilyAvailabledevices选项。创立设计文件：lpmInstalledPlug-Ins—>Storage—>lpm_shiftreg项在参数设置中，设置移位方向为左移，输入时钟使能端，输入数据，异步清零。VHDL程序：LIBRARYieee;USEieee.std_logic_1164.all;LIBRARYlpm;USElpm.all;ENTITYshiftregISPORT(aclrclockshiftinq);

:INSTD_LOGIC;:INSTD_LOGIC;:INSTD_LOGIC;:OUTSTD_LOGIC_VECTOR(7DOWNTO0)ENDshiftreg;ARCHITECTURESYNOFshiftregISSIGNALsub_wire0 :STD_LOGIC_VECTOR(7DOWNTO0);COMPONENTlpm_shiftregGENERIC(lpm_directionlpm_typelpm_width);

:STRING;:STRING;:NATURALPORT();

aclr:INSTD_LOGIC;clock :INSTD_LOGIC;q :OUTSTD_LOGIC_VECTOR(7DOWNTO0);shiftin :INSTD_LOGICENDCOMPONENT;BEGINq <=sub_wire0(7DOWNTO0);lpm_shiftreg_component:lpm_shiftregGENERICMAP(lpm_direction=>“RIGHT“,lpm_type=>“LPM_SHIFTREG“,lpm_width=>8)PORTMAP(aclr=>aclr,clock=>clock,shiftin=>shiftin,q=>sub_wire0);ENDSYN;27SEG译码器7segVHDL程序libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityseg_7isport(scan_clk,cnt_aclr:instd_logic;z0,z1,z2,z3,z4,z5,z6:instd_logic;seg7:outstd_logic_vector(6downto0);wei:outstd_logic_vector(6downto0));endseg_7;architecturertlofseg_7issignalseg_wire:std_logic;signalwei_wire:std_logic_vector(6downto0);typestis(k_0,k_1,k_2,k_3,k_4,k_5,k_6);signalst_nxt:st;beginscan_st:process(scan_clk,cnt_aclr,st_nxt)beginifcnt_aclr=”1”thenst_nxt<=k_0;elsif(scan_clk”eventandscan_clk=”1”)thencasest_nxtiswhenk_0=>st_nxt<=k_1;whenk_1=>st_nxt<=k_2;whenk_2=>st_nxt<=k_3;whenk_3=>st_nxt<=k_4;whenk_4=>st_nxt<=k_5;whenk_5=>st_nxt<=k_6;whenk_6=>st_nxt<=k_0;endcase;endif;endprocess;scan_o:process(st_nxt,z0,z1,z2,z3,z4,z5,z6)begincasest_nxtiswhenk_0=>seg_wire<=z0;wei_wire<=“0000001“;whenk_1=>seg_wire<=z1;wei_wire<=“0000010“;whenk_2=>seg_wire<=z2;wei_wire<=“0000100“;whenk_3=>seg_wire<=z3;wei_wire<=“0001000“;whenk_4=>seg_wire<=z4;wei_wire<=“0010000“;whenk_5=>seg_wire<=z5;wei_wire<=“0100000“;whenk_6=>seg_wire<=z6;wei_wire<=“1000000“;endcase;endprocess;seg7<=“1111110“whenseg_wire=”0”else“0110000“whenseg_wire=”1”;wei<=wei_wire;endr