简单四位微处理器设计

mail082543 一加深对EDA技术的理解。部RM的操该理与D产个微器2901兼容。四位R信号、四位S信号以及进位信号CIN，输出为F[3..0]、进位输出C4、进位生成信号G_BAR、进位传输信号P_BAR和溢出标志OVR。F[3..0]信号还反馈到寄存器和器。决定输出A、B的读出数据。当器写使能时，B信号还决定了数据的写入地址。RSAQAB0Q0B0ADADQD0ALU选择模块VHDL代码：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.NUMERIC_STD.ALL;ENTITYalumuxD,Q,A,B:INUNSIGNED(3DOWNTOALUIN_CTRL:INSTD_LOGIC_VECTOR(2DOWNTO0);R,S:BUFFERUNSIGNED(3DOWNTO0)ENDENTITYARCHITECTUREarc1OFalumuxISWITHALUIN_CTRLRAWHEN --R在ALU"0000"WHEN"010"|"011"|"100",DWHENOTHERS;WITHALUIN_CTRLS<=QWHEN" --S在ALUBWHEN"001"|"011",AWHEN"100"|"101","0000"WHENOTHERS;ENDARCHITECTURERORRAND(NOTR)ANDRXORNOT(RXORUSEUSEUSEIEEE.NUMERIC_STD.ALL;ENTITYaluISPORT(R,S:INUNSIGNED(3DOWNTOALU_CTRL:INSTD_LOGIC_VECTOR(2DOWNTO0);CIN:INSTD_LOGIC;F:BUFFERUNSIGNED(3DOWNTO0);G_BAR,P_BAR:BUFFERSTD_LOGIC;C4:BUFFERSTD_LOGIC;OVR:BUFFERSTD_LOGIC);ENDENTITYalu;ARCHITECTUREarc1OFaluSIGNALR1,S1,F1:UNSIGNED(4DOWNTO0);--实际运算时对五位输入数进行操作以获取进位R1 S1<='0'&S;CASEALU_CTRLISWHEN"000"IFCIN='0'THENF1<=R1+F1<=R1+S1+1;ENDIF;WHEN"001"IFCIN='0'F1<=S1+NOT(R1);F1<=S1+NOT(R1)+1;ENDIF;WHEN"010"IFCIN='0'F1<=R1+NOT(S1);F1<=R1+NOT(S1)+1;ENDIF;WHEN"011"=>F1<=R1ORS1; WHEN"100"=>F1<=R1ANDS1;WHEN"101"=>F1<=(NOTR1)ANDS1;WHEN"110"=>F1<=R1XORS1;WHEN"111"=>F1<=NOT(R1XORS1);WHENOTHERS=>F1<=" ENDCASE;ENDPROCESS;F<=F1(3DOWNTO C4<=F1(4);(R(3)ANDS(3))((R(3)ORS(3))AND(R(2)ANDS(2)))((R(3)ORS(3))AND(R(2)ORS(2))AND(R(1)ANDS(1)))((R(3)ORS(3))AND(R(2)ORS(2))AND(R(1)ANDS(1))AND(R(0)ANDS(0))));P_BAR<=NOT(R(3)ORS(3))AND(R(2)ORS(2))AND(R(1)ANDS(1))AND(R(0)ANDS(0)));OVR<='1'WHEN(F1(4)/=F1(3))ELSE'0';ENDARCHITECTUREarc1;RAM--USEUSEIEEE.NUMERIC_STD.ALL;ENTITYram1PORT(CLK:INRAM1_CTRL:INSTD_LOGIC_VECTOR(2DOWNTO0);RAM0,RAM3:INSTD_LOGIC;A,B:BUFFERUNSIGNED(3DOWNTO0));ENDENTITYram1;ARCHITECTUREarc1OFRAM1TYPERAM_TYPEISARRAY(15DOWNTO0)OFUNSIGNED(3DOWNTO0);--定义RAMSIGNALAB_DATA --16SIGNALCTRL:STD_LOGIC_VECTOR(1DOWNTO0);CTRL<= RAM1_CTRL(2)&RAM1_CTRL(1);PROCESS(CLK,Baddr)IF(CLK'EVENTANDCLK='1')THENCASECTRLIS "01"=>AB_DATA(TO_INTEGER(Baddr))<= "10"=>AB_DATA(TO_INTEGER(Baddr))<=RAM3&F(3DOWNTO1); "11"=>AB_DATA(TO_INTEGER(Baddr))<=F(2DOWNTO0)&ENDCASE --A.B，10RAM3与F前三位，11RAM0与FENDIFENDPROCESS<=AB_DATATO_INTEGERAaddrAaddr<=AB_DATATO_INTEGERBaddrBENDARCHITECTUREarc1;-----LIBRARYIEEEUSEIEEE.STD_LOGIC_1164.ALLUSEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.NUMERIC_STD.ALL;ENTITYqreg1PORT(CLK:INSTD_LOGICF:INUNSIGNED(3DOWNTO0)Q_CTRL:INSTD_LOGIC_VECTOR(2DOWNTO0);Q0,Q3:INOUTSTD_LOGIC;Q:BUFFERUNSIGNED(3DOWNTO0));ENDENTITYqreg1;ARCHITECTUREarc1 qreg1SIGNALQ_DATA:UNSIGNED(3DOWNTO0);IF(CLK'EVENTANDCLK='1')THEN CASEQ_CTRLIS "000"=>Q_DATA<=F; "100"=>Q_DATA<=Q3&Q(3DOWNTO1);--000寄存F数据，100寄存器右 "110"=>Q_DATA<=Q(2DOWNTO0)&Q0;--移，110左移，其余维持WHENOTHERS =>Q_DATA<=Q_DATA;ENDIF;ENDPROCESS;Q3F(3WHENQ_CTRL="110"ORQ_CTRL="111ELSEZ';--寄存器左移时Q0<=F(0)WHEN(Q_CTRL="100"ORQ_CTRL="101")ELSE'Z';--算结果信号F的最ENDARCHITECTUREarc1 FZZZZFZZZZAZZZZFZZZZFZZFZZFZZFZZLIBRARYUSEUSEIEEE.NUMERIC_STD.ALL;ENTITYoutmuxPORT(A,F:INUNSIGNED(3DOWNTO0)MUX_CTRL:INSTD_LOGIC_VECTOR(2DOWNTO0);OE:INSTD_LOGIC;Y:BUFFERUNSIGNED(3DOWNTO0))ENDENTITYARCHITECTUREarc1OF SIGNALY_DATA:UNSIGNED(3DOWNTO0); FYY_DATAWHEN ENDARCHITECTURE LIBRARYIEEEUSEIEEE.STD_LOGIC_1164.ALLUSEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.NUMERIC_STD.ALL; psIS COMPONENTalumux PORT(D,Q,A,B:INUNSIGNED(3DOWNTOALUIN_CTRL:INSTD_LOGIC_VECTOR(2DOWNTO0);R,S:BUFFERUNSIGNED(3DOWNTO0));ENDCOMPONENTalu PORT(R,S:INUNSIGNED(3DOWNTO0);ALU_CTRL:INSTD_LOGIC_VECTOR(2DOWNTO0);CIN:INSTD_LOGIC;F:BUFFERUNSIGNED(3DOWNTO0);G_BAR,P_BAR:BUFFERSTD_LOGIC;C4:BUFFERSTD_LOGIC;OVR:BUFFERSTD_LOGIC);ENDCOMPONENTram1 PORT(CLK:INSTD_LOGIC;Aaddr,Baddr,F:INUNSIGNED(3DOWNTO0);RAM1_CTRL:INSTD_LOGIC_VECTOR(2DOWNTO0);RAM0,RAM3:INOUTSTD_LOGIC;A,B:BUFFERUNSIGNED(3DOWNTO0));ENDCOMPONENT;COMPONENTqreg1 PORT(CLK:INSTD_LOGIC;F:INUNSIGNED(3DOWNTO0)Q_CTRL:INSTD_LOGIC_VECTOR(2DOWNTO0);Q0,Q3:INOUTSTD_LOGIC;Q:BUFFERUNSIGNED(3DOWNTO0));ENDCOMPONENT;COMPONENToutmux PORT(A,F:INUNSIGNED(3DOWNTO0);MUX_CTRL:INSTD_LOGIC_VECTOR(2DOWNTO0);OE:INSTD_LOGIC;Y:BUFFERUNSIGNED(3DOWNTO0));ENDCOMPONENT; psLIBRARYUSEUSEIEEE.NUMERIC_STD.ALL; ENTITYcpu4PORTCLKIN Aaddr,Baddr:INUNSIGNED(3DOWNTO0);D:INUNSIGNED(3DOWNTO0);CIN:INSTD_LOGIC;OE:INSTD_LOGIC;Q0,Q3:INOUTSTD_LOGIC;Y:BUFFERUNSIGNED(3DOWNTO0);G_BAR,P_BAR:BUFFERSTD_LOGIC;C4:BUFFERSTD_LOGIC;OVR:BUFFERSTD_LOGIC;F_0:BUFFERSTD_LOGIC;F_3:BUFFERSTD_LOGIC)ENDENTITYcpu4ARCHITECTUREarc1 cpu4SIGNALALUIN_CTRL:STD_LOGIC_VECTOR(2DOWNTO0):=I(2DOWNTO0);SIGNALALU_CTRL:STD_LOGIC_VECTOR(2DOWNTO0):=I(5DOWNTO3);SIGNALRAM1_CTRL:STD_LOGIC_VECTOR(2DOWNTO0):=I(8DOWNTO6);SIGNALQ_CTRL:STD_LOGIC_VECTOR(2DOWNTO0):=I(8DOWNTO6);SIGNALMUX_CTRL:STD_LOGIC_VECTOR(2DOWNTO0):=I(8DOWNTO6);SIGNALA,B:UNSIGNED(3DOWNTO0); SIGNALQ:UNSIGNED(3DOWNTO0);SIGNALR,S:UNSIGNED(3DOWNTO0);SIGNALF:UNSIGNED(3DOWNTO0); U1:ram1 U2:qreg1PORTMAP(CLK,F,Q_CTRL,Q0,Q3,Q);U3:alumuxPORTMAP(D,Q,A,B,ALUIN_CTRL,R,S)U4:alu PORTMAP(R,S,ALU_CTRL,CIN,F,G_BAR,P_BAR,C4,OVR);U5:outmuxPORTMAP(A,F,MUX_CTRL,OE,Y);F_3<=F(3