集成电路课件

集成电路分析与设计第1讲认识集成电路设计及其设计过程2023/2/61《集成电路分析与设计》课程主要介绍什么内容?CMOS数字集成电路(CMOSdigitalIC)IC的发展历史及现状(HistoryofIC)IC设计流程和方法(DesignprocessandMethodology)IC制造工艺技术(Fabricationprocess)ICEDA（CAD）工具使用(EDAtools)CMOS反相器设计(CMOSInverter)CMOS组合逻辑门设计(CombinationalLogicCircuit)CMOS时序逻辑电路设计(SequentialLogicCircuit)IC版图设计(Layout)IC仿真技术(Simulation)存储器电路设计介绍(MemoryCircuits)模拟IC设计介绍(AnalogIC)2023/2/62《集成电路分析与设计》课程信息课程性质：是一门专业基础课程主要介绍CMOS数字集成电路设计的基础知识共40课时（32理论课时+8实验课时）完成4个实验对准备从事IC行业的学生来讲，本课程只是一个基础，还需要继续深入学习更多关于IC设计的知识，如数字IC深入，模拟IC，RFIC等。2023/2/63Project（选作内容）完成一个44SRAM芯片的设计3人一组项目过程：A期中OralpresentationB期末OralpresentationC项目报告书一份D3人项目成绩相同2023/2/65GradingPolicy课堂提问和作业10%实验20%考试（开卷）70%规则：（1）1个问题和4次作业，每次/个2分，共10分；（2）每个实验完成得5分，共20分；（3）点名1次不到，10分没了；（4）抄作业，抄实验报告，相应分数没了；（5）请假规则：必须有正规请假手续和课前请假。2023/2/66

本课程推荐书目

教材中文版周润德等译，数字集成电路设计透视第二版，电子工业出版社(JanM.Rabaey,etal.DigitalIntegratedCircuits,2nde,PrenticeHall,2004)参考书Sung-Mo(Steve)Kang,YusufLeblebici,CMOSDigitalIntegratedCircuitsAnalysis&Design,3rdEdition,McGraw-Hill2003R.JacobBaker,CMOSCircuitDesign,Layout,andsimulation,3rdEdition,Wiley,2010韩雁，集成电路设计CAD/EDA工具实用教程，机械工业出版社，20102023/2/67几个常见缩略词CMOS(complementarymetaloxidesemiconductor)IC(integratedcircuit)VLSI(verylargescaleintegrated)ULSI(ultra-largescaleintegrated)MOSFET(metaloxidesemiconductorfieldeffecttransistors)SPICE(simulationprogramwithintegratedcircuitemphasis)2023/2/69认识集成电路和集成电路设计为什么需要集成电路？与以前的集成电路设计相比，为什么现在的集成电路设计出现了不同以及现在的集成电路设计遇到了哪些新的挑战？未来，集成电路将如何发展？2023/2/610为什么需要集成电路?Integrationreducesdevicesize（减小尺寸）Laptop,iPod,mp3,cellphone,...Integrationimprovesthedesign（提高性能）higherspeed;lowerpowerconsuption;morereliable.Integrationreducesmanufacturingcost（降低成本）BOM(BoardofMaterials)costreducesMassICproductionreducescost2023/2/611Moore’sLaw(1965)GordonMoore–IntelFounder“Thenumberoftransistorsonachipdoubledevery18to24months.”Electronics,April19,1965.GordonMooreIntelCo-FounderandChairmainEmeritusImagesource:IntelCorporation2023/2/613InformationRevolutionElectronicsystemincars.Electronicfinancialsystem:e-banking,e-money,e-stock,RFIDlablePersonalcomputing/entertainmentMedicalelectronicsystems.Internet:routers,firewalls,servers,storagesElectroniclibrary(Google,...)DVDR/W,HDTV,InteractiveTVIngeneral,consumerelectronicsetc...2023/2/614ChallengesofICDesignComplexity:Multi-milliontransistorsonasinglechip(smallersize/fasterspeed)Multipleandconflictingspecificationsforhighperformance(power/speed/throughput)Competition:ShortdesigntimeDesignTools:Multipletoolsinvolved,ComplexdesignflowAnalogBasebandDigitalBaseband(DSP+MCU)PowerManagementSmallSignalRFPowerRF2023/2/6152023/2/617TheTransistorRevolutionFirsttransistorBellLabs,1947J.Bardeen,W.Shockley,andW.Brattain(1956NobelprizeLaureate)2023/2/6181958年J.Kilby（TI）研制成功第一个集成电路1959年R.Noyce（Fairchild）第一个利用平面工艺制成集成电路TheFirstIntegratedCircuits2023/2/619

Intel4004Micro-Processor19702300transistors~1MHzoperation2023/2/621IntelPentium(IV)microprocessorPentium®4“Northwood”CommercialProduction:Year2001L=0.13µm6MLCuLow-kFC-PGA22023/2/622MOSFETTechnologyMOSFETtransistor-Lilienfeld(Canada)in1925andHeil(England)in1935CMOS–1960’s,butplaguedwithmanufacturingproblems(usedinwatchesduetotheirpowerlimitations)PMOSin1960’s(calculators)NMOSin1970’s(4004,8080)–forspeedCMOSin1980’s–preferredMOSFETtechnologybecauseofpowerbenefitsBiCMOS,Gallium-Arsenide,Silicon-GermaniumSOI,Copper-LowK,strainedsilicon,High-kgateoxide...2023/2/6231’’Waferin1964vs.300mm(12”)Waferin20032023/2/625IBMPowerPC970(130nm)20031.8Ghz58M118mm2ApplePowerG5,thefastestPCin2003,hasdualPPC970CPU2023/2/626TwochipsyouareseeingtodayMicroprocessorASIC(ApplicationSpecificIC)2023/2/627State-of-theArt:LeadMicroprocessors(uptodate)

Pentium4180nm(2001)1.7GHz42Mtransistors217mm2Pentium4130nm(2003)3.2GHz55MTransistors131mm2Pentium490nm(2004)3.4Hz125MTransistors112mm2Pentiumon65nm(2005/2006)250Million

Pentiumon45nm(2007)400to500Million(Alluse0.13umtechnologyexceptPentium4–Prescott,whichuses90nmtech)2023/2/629State-of-theArt:LeadMicroprocessors(uptodate)300mmwaferandPentium4IC.PhotoscourtesyofIntel.2023/2/630WhatADigitalDesignerNeedstoKnow...

“MicroscopicProblems”•Ultra-highspeeddesignInterconnect•Noise,Crosstalk•Reliability,Manufacturability•PowerDissipation•Clockdistribution.

“MacroscopicIssues”•Time-to-Market•MillionsofGates•High-LevelAbstractions•Reuse&IPAvailability•systemsonachip(SoC)

•Predictability•etc.2023/2/6312023/2/6322023/2/6332023/2/6342023/2/6352023/2/6362023/2/6372023/2/638>95%2023/2/639如何设计一个集成电路？2023/2/6402023/2/641TheVLSIdesignprocess工程的艺术Maybepartoflargerproductdesign.Majorlevelsofabstraction:specificationarchitecturelogicdesigncircuitdesignlayoutdesign2023/2/642MajorSegmentsofICIndustryFablessDesignHousesEDAToolsCompaniesDesignServiceCompaniesLibrary&IPProvidersDedicatedICManufacturers(Foundry)Post:EDA:ElectronicDesignAutomationIP:siliconIntellectualPropertyIDM:IntegratedDeviceManufacturerIntegratedservicePackaging&TestingHouses2023/2/643ASICDesignStylesFullCustomDesignFlowCircuitiscreatedbycomposingatransistornetlistSPICEsimulationisperformedtoverifythecircuitKnownas“capture-and-simulate”paradigmLayoutismostlydonemanuallyPopularforhigh-performancemicroprocessors&memoriesCell-BasedSynthesisFlowDesignisfirstdescribedbyHardwareDescriptionLanguage(e.g.,VerilogandVHDL)Basedonacelllibrary,netlistiscreatedbysynthesistoolsKnownas“describe-and-synthesize”paradigmLayoutcanbedonethroughautomatictools2023/2/644DetailedCustomDesignFlowBlockSpecification(FiniteStateMachine,ArithmeticExpression,BooleanExpression)LogicDesignGate-LevelNetlistTransistorNetlistTechnologyMappingSPICESimulationSPICEModelLayoutDesignLayoutLayoutRulesDesignRuleChecking(DRC)Layoutvs.SchematicCheck(LVS)Parasitic(orwiring)RCextractionPost-LayoutSPICESimulationCheckifSPECismet?Ifyes,done.Otherwise,gobacktooptimizethedesign2023/2/645ASimpleExample FunctionalityOne-bitbinaryfull-adderTechnology1mmn-wellCMOStechnologySpeedInputtooutputdelay<5nsArea<3000mm2PowerDissipation<1mWat5voltsand200MHzFull-adderABSumCarry_outSum=A⊕B⊕C=ABC+ABC+ABC+ACBCarry_out=AB+BC+CA(majorityfunction)BooleanDescriptionC2023/2/646LogicDesignLogicminimizationtrick:Thecarry_outsignalisusedtorealizethefunctionofsignalsum

inordertoreducetheoverallcircuitsize.Today’slogicsynthesistools(suchasDesignCompiler)incorporatingsomeadvancedalgorithms,isabletoperformautomaticlogicminimization.x=Carry_out#of‘1’sInA,B,C

Carry_out

Sum012300110101(A+B+C)x=>exactlyoneofA,B,Cis‘1’2023/2/647Transistor-LevelSchematicTechnologymappingManysimpleANDORgatesaremergedintoacomplexgate(oracellinthecelllibrary)TransistoraspectratiopMOS(W/L)isusuallylargerthannMOS(W/L),e.g.,2:1xyxyx=(AB+BC+CA)y=(A+B+C)x+ABC)2023/2/648InitialLayoutPost-layoutSPICEsimulationincludesthe“parasiticresistance&capacitance”ismoreaccuratethanthepre-layoutsimulation(pre-sim)Ratioofchannelwidths2:12023/2/649I/OSimulationWaveformsPropagationtimetPHLortPLHasdefinedaboveLow-to-highpropagationtime（传播延时）tPLH=8.2ns!

Gottogobacktooptimizethedesign!!!C(Carry_in)Sum2023/2/650OptimizedLayoutTransistorSizingchangestheaspectratios

(W/L)ofselectedtransistorsAlargeraspectratiomayleadtoahigherspeedWireSizingisalsomorerecentlyproposedPropagationDelay<5ns!2023/2/651FullCustomDesignExample（another)A/DPLAI/OcompRAMMetal1ViaMetal2I/OPadRandomlogic(standardcelldesign)2023/2/652Cell-BasedDesignFlowArchitecturedesignSystem-levelintegrationlayoutNoviolationMemorymoduleFunctionalmodelTestbenchRTLcoding&simulationRTLcodeCellLibrarysynthesisviewRTL-synthesis(DesignCompiler)NetlistphysicalviewPlace&Route(Apollo)LayoutviolationPost-LayoutTimingCheck(DesignTime)SDFSDF:standarddelayformat2