北科自动化数电pp6

CHAPTER6FunctionsofCombinationalLogic6-1BasicAdders6-2ParallelBinaryAdders并行二进制加法器

6-3Comparators比较器6-4Decoders译码器6-5Encoders编码器6-6CodeConverters代码转换器

6-7Multiplexers(DataSelectors)数据选择器/多路复用（MUX）6-8Demultiplexers多路分用器/解双工器（DEMUX）

6-9ParityGenerator/Checker奇偶校验器IntroductiontoSeveralMSICombinationalCircuits介绍几种常用的中规模组件 Inthischapteryoushouldknow:TheinternalfunctionalprincipleofeveryMSIchips(inbrief)ThoseMSIchipsarecombinationalcircuit(thatmeanstheyarecomposedoflogicgates);youshouldlearnhowtousethemFocusonthesetwoblocksnameddecoderanddataselectorwhichcanbeusedtoproducesomegivenlogicfunction6-1BasicAdders

(implementing1-bitaddition)

基本加法器6-1-1Half-Adder半加器6-1-2Full-Adder全加器

6-1-3Fulladderfromtwohalf-addercircuitsGeneralrulesofbinaryaddition：a.Produceacarrybitwheneverwehave2b.LSBaddition:withoutconsideringthecarrybit。c.Whenprocessingtheotherbits,weshouldacceptthreenumbers(twoinputbitsandacarrybit)d.Anytwobitswillproduceasumbitandaoutputcarrywhenbeadded.Half-adderFull-adder6-1-1Half-Adder(半加器)Howcouldweimplementthisfunctionusinglogiccircuit?Ahalf-adderisacombinationallogiccircuitthataddtogethertwoone-bitvaluesandproducesasumandacarryoutput.Thehalfpartofthenamecomesfromthelackofacarryinput.0+0=00+1=11+0=11+1=10ZeropluszeroequalszeroZeroplusoneequalsoneOnepluszeroequalsoneOneplusoneequalszerowithacarryofoneSimpleBinaryAdditionAfull-adderisacombinationallogiccircuitthataddstwoone-bitvaluesplusacarrybitandproducesasumandacarryoutput.Thefullpartofthenamecomesfromthecarryinputbit.6-1-2Full-Adder全加器

TruthtableSketchtheinternallogiccircuitoffull-adderaccordingtothebooleanexpression.6-1-3Fulladderfromtwohalf-addercircuits

6-2ParallelBinaryAdders

(implementingmore-bitaddition)

并行二进制加法器

6-2-1Two-bitparallelbinaryadder6-2-2Four-bitparallelbinaryadder

Howcouldan-bitparalleladderbeconstructed?An-bitadderrequiresn-1full-addersandonehalf-adder.Howcouldafull-adderbefunctionedasahalf-adder?6-2-1Two-bitparallelbinaryadderUsingtwofull-adderstoimplementA2A1+B2B1

thepinsofdouble-full-adderSN74LS183114SN74LS1831an1bn1cn-11cn1sn2cn-12cn2sn2an2bnUccGND6-2-2Four-bitparallelbinaryadder

四位并行二进制加法器ripplecarry（串行进位）addershowing“worst-case”carrypropagationdelays.

CascadingFull-Adders串行全加器Look-AheadCarryadder:超前进位加法器：Carrygeneration:CgCarrypropagation:CpP191fourfull-addersoutputequation.4位超前进位加法器74LS283内部结构Anotherapplicationofadder:Avotingsystem6-3Comparators

数值比较器Acomparatorsisacombinationallogiccircuitthatcomparestwobinaryinputvaluesandproducesresultsthatspecifytherelativevalueofoneinputwithrespecttotheother.OutputsofsomecomparatorsspecifywhetherA=B,othersmayspecifyA=B,A>BandA<B.Wewillfocusonthesecondcomparators.BinaryComparators二进制比较器Functiondescription1-BitComparator&&1ABA<BA>BA=BABA>BA<BA=BLogicdiagramLogicsymbolComparingprinciple：1.先从高位比起，高位大的数值一定大。2.若高位相等，则再比较低位数，最终结果由低位的比较结果决定。more-BitComparatorTruthtableforfour-bitcomparatora3>b3

100a3=b3a2=b2a1=

b1a0=b0

010a3=b3a2=b2a1=

b1a0<b0

001a3=b3a2=b2a1=

b1a0>b0

100a3=b3a2=b2a1<b1

001

a3=b3a2=b2a1>

b1

100a3=b3a2<b2

001a3=b3a2>b2

100a3<b3

001

input

output

a3b3a2b2a1b1a0b0

LES

(A>B)(A=B)(A<B)根据比较规则，可得到四位数值比较器逻辑式：A=B:A<B:AB:Pindiagramandlogicsymbolforthe74HC854-bitmagnitudecomparator.A=B:A<B:AB:例1：七位二进制数比较器。（采用两片85）“1”必接好（A>B）L（A<B）LA>BA=BA<BA1B1A0B0A3B3A2B2（A=B）L74LS85（A>B）L（A<B）LA>BA=BA<BA1B1A0B0A3B3A2B2（A=B）L74LS85(1)(2)a3a2a1a0a6a5a4Ab3b2b1b0b6b5b4B高位片低位片6-5Encoders

编码器EncodersAnencoderisacombinationallogiccircuitthataccepts2n

binaryinputsandproducesndataencodedoutputvalues.An8-to-3encoderhaseightinputlinesandthreeoutputlines.Whenoneofthedatainputsisactive,theoutputcodethatrepresentsthatvalueisgenerated.8-line-to-3-lineencoder（8线-3线编码器）

2priorityencoder(优先编码器)3Decimal-to-BCDencoder（二－十进制编码器）8-line-to-3-lineencoder设八个输入端为I1I8，八种状态，与之对应的输出设为F1、F2、F3，共三位二进制数。设计编码器的过程与设计一般的组合逻辑电路相同，首先要列出状态表（即真值表），然后写出逻辑表达式并进行化简，最后画出逻辑图。Truthtable(active-lowinput)I1I2I3I4I5I6I7I8&&&F3F2F1LogicdiagramPriorityencoder(优先编码器)Logicdiagramof74LS148选通输入端选通输出端扩展端Functiondescription1XXXXXXXX11111

01111111111101

0XXXXXXX0

00010

0XXXXXX01

00110

0XXXXX011

01010…………

001111111

11110Functiontableof74LS148Example:用两片74LS148接成16线－4线优先编码器二十进制编码器的作用：将十个状态（对应于十进制的十个代码）编制成BCD码。十个输入需要几位输出？四位输入：I0I9输出：F4

F1Decimal-to-BCDencoderLogicsymbolforadecimal-to-BCDencoder.

TruthtableActive-lowinputPindiagramandlogicsymbolforthe74HC147decimal-to-BCDpriorityencoder(HPRImeanshighestvalueinputhaspriority).

Application:Asimplifiedkeyboardencoder.

Assignments:(duetonextMonday)P2326、8、12补充作业题：用4片74LS148组成32线－5线优先编码器，允许附加必要的门电路。6-4Decoders

译码器6-4-1Binarydecoder（二进制译码器）6-4-2BCD-to-decimaldecoder（BCD码-十进制译码器）6-4-3BCD-to-7-segementdecoder（BCD码-七段显示驱动译码器）6-4-1Binarydecoder二进制译码器的作用：将n种输入的组合译成2n种电路状态。也叫n2n线译码器。译码器的输入——一组二进制代码译码器的输出——一组高低电平信号Binaryinputs

Active-lowoutputs4-line-to-16-linedecoderWhatdoyoufigureoutfromtheabovetruthtable?n-2n

线译码器，包含了n变量所有的最小项。加上或门或与非门，可以组成任何形式的输入变量小于n的组合逻辑函数。若要产生多输出逻辑函数时,使用译码器+门电路较有利。tip例：用2-4线译码器产生一组多输出函数。接线图11Z2Z1练习题：用74LS138译码器和门电路产生如下多输出逻辑函数。3-line-to-8-line74LS138decoder译码器的多片扩展利用译码器的使能控制端可以将多片n-2n线译码器组成（n+1）-2（n+1）线译码器或更大的译码器。例：用两片74LS138接成4线－16线译码器6-4-2BCD-to-decimaldecoder二十进制编码显示译码器显示器件在数字系统中，常常需要将运算结果用人们习惯的十进制显示出来，这就要用到专门的显示译码器。显示器件：常用的是七段显示器件。6-4-3BCD-to-7-segementdecoderLED:light-emittingdiode发光二极管LCD:liquidcrystaldisplay液晶显示器Arrangementsof7-segmentLEDdisplays.

abcdfgabcdefg111111001100001101101e七段显示器件的工作原理：Step1.The1saremappeddirectlyfromtheabovetable.Step2.Allofthe“don’tcare”areplacedonthemap.Step3.The1saregroupedasshownP144figure4-46MinimumSOPlogicexpressionforthesegment-a.显示译码器：11474LS49BCBIDAeabcdfgUccGND74LS49的管脚图消隐控制端74LS49的功能表（简表）输入输出显示DABIag10XXXX0000000消隐8421码译码显示字型74LS49与七段显示器件的连接：74LS49是集电极开路，必须接上拉电阻bfacdegbfacdegBIDCBA+5V+5V关于OC门的介绍：/shudian/netpages/dig2_2.htm6-8Multiplexers(DataSelectors)

多路复用器/数据选择器（MUX）AMUXisadevicethatallowsdigitalinformationfromseveralsourcestoberoutedontoasinglelinefortransmissionoverthatlinetoacommondestination.Thebasicmultiplexerhasseveraldata-inputlinesandasingleoutputline.从一组数据中选择一路信号进行传输的电路，称为数据选择器。6-7-14-inputmultiplexer6-7-2Expandedmultiplexers6-7-3Multiplexerasalogicfunctiongenerator控制信号输入信号输出信号数据选择器类似一个多路开关。选择哪一路信号由相应的一组控制信号控制。A0A1D3D2D1D0W6-7-14-inputmultiplexer4-inputmultiplexerWaveform

双4选1数据选择器74LS153功能表控制端：为或，低电平有效。选择端A1A0

：为两个4选1数据选择器共用。其中例：用一片74LS153组成8选1:A2=0:(1)工作；A2=1:(2)工作。D1D7D0D2D3D4D5D6Y1D01D11D21D32D02D12D22D374LS153(1)(2)BAA2(低位）(高位）A0A1选择信号（三位）16-7-2Expandedmultiple