第3章-VHDL设计初步-习题

习题3-2图3-16所示的是4选1多路选择器，试分别用IF_THEN语句、WHEN_ELSE和CASE语句的表达方式写出此电路的VHDL程序，要求选择控制信号s1和s0的数据类型为STD_LOGIC；当s1='0'，s0='0'；s1='0'，s0='1'；s1='1'，s0='0'和s1='1'，s0='1'时，分别执行y<=a、y<=b、y<=c、y<=d。

习题3-2WHEN_ELSE条件信号赋值语句

LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux41ISPORT(s0,s1:instd_logic;a,b,c,d:instd_logic;y:outstd_logic);ENDENTITYmux41;ARCHITECTUREbehave1OFmux41ISSIGNALs:std_logic_vector(1downto0);BEGINS<=s1&s0;y<=aWHENs="00"ELSE bWHENs="01"ELSE cWHENs="10"ELSE dWHENs="11"ELSE '0';ENDbehave1;多选择控制的IF语句

IF条件1THEN<顺序语句l>;ELSIF条件2THEN<顺序语句2>;…..ELSIF条件nTHEN<顺序语句n>;ELSE<顺序语句n+1>;ENDIF;…ARCHITECTUREbehave2OFmux41ISSIGNALs:std_logic_vector(1downto0);BEGINs<=s1&s0;PROCESS(s,a,b,c,d)BEGINIFs="00"THENy<=a;ELSIFs="01"THENy<=b;ELSIFs="10"THENy<=c;ELSEy<=d;ENDIF;ENDPROCESS;ENDbehave2;CASE语句…ARCHITECTUREbehave3OFmux41ISSIGNALs:std_logic_vector(1downto0);BEGINs<=s1&s0;PROCESS(s,a,b,c,d)BEGINCASEsISWHEN"00"=>y<=a;WHEN"01"=>y<=b;WHEN"10"=>y<=c;WHEN"11"=>y<=d;WHENOTHERS=>y<='0';ENDCASE;ENDPROCESS;ENDbehave3;习题3-3图3-17所示的是双2选1多路选择器构成的电路MUXK，对于其中MUX21A，当s='0'和s='1'时，分别有y<='a'和y<='b'。试在一个结构体中用两个进程来表达此电路，每个进程中用CASE语句描述一个2选1多路选择器MUX21A。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmuxkISPORT(a1,a2,a3:instd_logic;s0,s1:instd_logic;outy:outstd_logic);ENDENTITYmuxk;ARCHITECTUREbehaveOFmuxkISSIGNALtmp:std_logic;SIGNALoutx:std_logic;BEGINPr1:PROCESS(a2,a3,s0)BEGINCASEs0ISWHEN'0'=>tmp<=a2;WHEN'1'=>tmp<=a3;WHENOTHERS=>tmp<='0';ENDCASE;ENDPROCESS;Pr2:PROCESS(a1,tmp,s1)BEGINCASEs1ISWHEN'0'=>outx<=a1;WHEN'1'=>outx<=tmp;WHENOTHERS=>outx<='0';ENDCASE;ENDPROCESS;outy<=outx;ENDbehave;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21aISPORT(a,b:instd_logic;s:instd_logic;y:outstd_logic);ENDENTITYmux21a;ARCHITECTUREbehaveOFmux21aISBEGINy<=aWHENs='0'ELSEb;ENDbehave;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmuxkISPORT(a1,a2,a3:instd_logic;s0,s1:instd_logic;outy:outstd_logic);ENDENTITYmuxk;ARCHITECTUREbehaveOFmuxkISSIGNALtmp:std_logic;COMPONENTmux21aPORT(a,b,s:instd_logic;y:outstd_logic);ENDCOMPONENT;BEGINu1:mux21aPORTMAP(a2,a3,s0,tmp);u2:mux21aPORTMAP(a1,tmp,s1,outy);ENDbehave;必须先编译、调试子模块，才能使用元件例化语句。

习题3-6图3-18是一个含有上升沿触发的D触发器的时序电路，试写出此电路的VHDL设计文件。

LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux_dISPORT(CL,CLK0:instd_logic;OUT1:outstd_logic);END;ARCHITECTUREbehaveOFmux_dISSIGNALx,y:std_logic;BEGINx<=NOT(CLORy);--或x<=CLNORyOUT1<=NOTy;PROCESS(CLK0)BEGINIFCLK0'EVENTANDCLK0='1'THENy<=x;ENDIF;ENDPROCESS;ENDbehave;4-5.给出1位全减器的VHDL描述。要求：(1)首先设计1位半减器，然后用例化语句将它们连接起来，图4-20中h_suber是半减器，diff是输出差，s_out是借位输出，sub_in是借位输入。(2)以1位全减器为基本硬件，构成串行借位的8位减法器，要求用例化语句来完成此项设计(减法运算是x–y-sun_in=diffr)。图4-19时序电路图

t0t1t2(1)先设计一个半减器Libraryieee;useieee.std_logic_1164.alll;Entityh_suberisPort(x,y:instd_logic;diff,s_out:outstd_logic);endh_suber;Architecturebehavofh_suberisBeginprocess(x,y)begindiff<=xxory;s_out<=(notx)andy;Endprocess;Endbehav;x、y00011011diff0110S_out0100一位全减器的VHDL描述suber.vhdLibraryieee;useieee.std_logic_1164.alll;EntitysuberisPort(x,y,sub_in:instd_logic;diffr,sub_out:outstd_logic);Endsuber;ArchitecturebehavofsuberisComponenth_suberPort(x,y:instd_logic;diff,s_out:outstd_logic);Endcomponent;Signalt0,t1,t2:std_logic;Beginu1:h_suberportmap(x=>x,y=>y,diff=>t0,s_out=>t1);u2:h_suberportmap(x=>t0,y=>sub_in,diff=>diffr,s_out=>t2);Sub_out<=t1ort2;Endbehav;(2)8位全减器(生成语句第九章)Libraryieee;useieee.std_logic_1164.alll;Entitysuber8isPort(a,b:instd_logic_vector(7downto0);Sin:instd_logic;sout:outstd_logic;C:outstd_logic_vector(7doento0);Endsub8;Architecturebehavofsuber8isComponentsuberPort(x,y,sub_in:instd_logic;diffr,sub_out:outstd_logic);Endcomponent;Signalstmp:std_logic_vector(8downto0);Beginstmp(0<=sin;Sout<=stmp(8);Gensub:foriin0to7generateu1:subportmap(x=>a(i),y=>b(i),diffr=>c(i),sub_out=>stmp(i+1));Endgenerate;end;习题3-4将3-20程序的计数器改为12进制计数器，程序用例3-21的方式表述，并且将复位RST改为同步清0控制，加载信号LOAD改为异步控制方式。讨论例3-20与例3-21的异同点。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT12ISPORT(CLK,RST,EN,LOAD:INSTD_LOGIC;DATA:INSTD_LOGIC_VECTOR(3DOWNTO0);DOUT:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);END;ARCHITECTUREbehavOFCNT12ISSIGNALQ:STD_LOGIC_VECTOR(3DOWNTO0);BEGINREG:PROCESS(CLK,LOAD)BEGIN

IFLOAD='0'THENQ:=DATA; ELSIFCLK'EVENTANDCLK='1'THEN IFEN='1'THEN

IF(RST='0')THENQ:=(OTHERS=>'0');

ELSEIFQ<11THENQ:=Q+1;ELSEQ:=(OTHERS=>'0');ENDIF;ENDIF; ENDIF; ENDIF;ENDPROCESS;COM:PROCESS(Q) IFQ="1011"THENCOUT<='1'; ELSECOUT<='0'; ENDIF;ENDPROCESS;DOUT<=Q;ENDbehav;习题准备：设计含有异步清零和计数使能的16位二进制加法可控计数器。LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_unsigned.all;USEieee.std_logic_arith.all;ENTITYex3_4_aISport(clk:instd_logic;clr,en:instd_logic;cnt:outstd_logic_vector(15downto0));END;ARCHITECTUREbhvOFex3_4_aIS signalcnt_tmp:std_logic_vector(15downto0); BEGIN process(clk,clr)begin

ifclr='1'thencnt_tmp<=(others=>'0');

elsif(rising_edge(clk))thenifen='1'thencnt_tmp<=cnt_tmp+1;endif;

endif;endprocess;cnt<=cnt_tmp;END;习题3-5设计含有异步清零和计数使能的16位二进制加减法可控计数器。LIB