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SOPCBuilderUserGuideInnovationDriveSanJose,CASOPCBuilderUserGuideInnovationDriveSanJose,CA95134Subscribe©2010AlteraCorporation..ALTERA,ARRIA,CYCLONE,,©2010AlteraCorporation..ALTERA,ARRIA,CYCLONE,,MAX,MEGACORE,NIOS,QUARTUSandSTRATIXareReg.U.S.Pat.&Tm.Off.and/ortrademarksofAlteraCorporationintheU.S.andothercountries.Allothertrademarksandservicemarksarethepropertyoftheirrespectiveholdersasdescribedat.AlterawarrantsperformanceofitssemiconductorproductstocurrentspecificationsinaccordancewithAltera’sstandardwarranty,butreservestherighttomakechangestoanyproductsandservicesatanytimewithoutnotice.Alteraassumesnoresponsibilityorliabilityarisingoutoftheapplicationoruseofanyinformation,product,orservicedescribedhereinexceptasexpresslyagreedtoinwritingbyAltera.Alteracustomersavisedtoobtainthelatestversionofdevicespecificationsbeforerelyingonanypublishedinformationandbeforeplacingordersforproductsorservices.SOPCBuilderUserGuideDecember2010AlteraCorporationContentsChapter1.IntroductiontoSOPCBuilderArchitectureofSOPCBuilderSystems 1–1SOPCBuilderModules 1–2FunctionsofSOPCBuilder 1–5DefiningandGeneratingtheSystemHardware 1–5CreatingaMemoryContentsChapter1.IntroductiontoSOPCBuilderArchitectureofSOPCBuilderSystems 1–1SOPCBuilderModules 1–2FunctionsofSOPCBuilder 1–5DefiningandGeneratingtheSystemHardware 1–5CreatingaMemoryMapforSoftwareDevelopment 1–6CreatingaSimulationM andTestBench 1–6SOPCBuilderDesignFlow 1–6VisualizationofSOPCBuilderSystems 1–8OperatingSystemSupport 1–8TalkbackSupport 1–8Chapter2.SystemInterconnectFabricforMemory-MappedInterfacesHigh-LevelDescription 2–1FundamentalsofImplementation 2–3FunctionsofSystemInterconnectFabric 2–3AddressDecoding 2–3DatapathMultiplexing 2–4WaitStateInsertion 2–5PipelinedTransfers 2–6DynamicBusSizingandNativeAddressAlignment 2–6DynamicBusSizing 2–7NativeAddressAlignment 2–8ArbitrationforMultimasterSystems 2–9TraditionalSharedBusArchitectures 2–9Slave-SideArbitration 2–10Arbiters 2–11ArbitrationRules 2–12BurstAdapters 2–14Interrupts 2–15IndividualRequestsIRQScheme 2–15PriorityEncodedInterruptScheme 2–15AssigningIRQsinSOPCBuilder 2–16ResetDistribution 2–16Chapter3.SystemInterconnectFabricforStreaInterfacesHigh-LevelDescription 3–1AvalonStreaandAvalonMemory-MappedInterfaces 3–2Adapters 3–3DataFormatAdapter 3–4Adapter 3–4ChannelAdapter 3–5ErrorAdapter 3–5MultiplexerExamples 3–5ExampletoDoubleClockFrequency 3–6ExampletoDoubleDataWidthandMaintainFrequency 3–6ExampletoBoosttheFrequency 3–6SOPCBuilderUserGuideiiContentsChapter4.SOPCBuilderComponentsComponentProviders 4–1ComponentHardwareStructure 4–2ComponentiiContentsChapter4.SOPCBuilderComponentsComponentProviders 4–1ComponentHardwareStructure 4–2ComponentInstancesInsidetheSOPCBuilderSystem 4–2ComponentsOutsidetheSOPCBuilderSystem 4–3ExportedConnectionPoints—ConduitInterfaces 4–3SOPCBuilderComponentSearchPath 4–4InstallingAdditionalComponents 4–4CopytotheIPRootDirectory 4–5ReferenceComponentsinan.ipxFile 4–6UnderstandingIPXFileSyntax 4–7UpgradingfromEarlierVersions 4–8ComponentStructure 4–8ComponentDescriptionFile(_hw.tcl) 4–9ComponentFileOrganization 4–9ComponentVersioning 4–9ClassicComponentsinSOPCBuilder 4–10Chapter5.UsingSOPCBuilderwiththeQuartusIISoftwareQuartusIIIPFile 5–1QuartusIIIncrementalCompilation 5–1TimeQuestAnalyzer 5–2AnalyzingPLLs 5–2AnalyzingSlowAsynchronousI/OPaths 5–3AnalyzingSingleDataRateSDRAMandSSRAM 5–4AnalyzingTristateBridgesandAsynchronousDevices 5–6AnalyzingDDRandDDR2Memories 5–7Chapter6.ComponentEditorComponentHardwareStructure 6–1StartingtheComponentEditor 6–2HDLFilesTab 6–2Bottom-UpDesign 6–2Top-DownDesign 6–3SignalsTab 6–3NaSignalsforAutomaticTypeandInterfaceRecognition 6–4TemplatesforInterfacestoExternalLogic 6–5InterfacesTab 6–6HDLParametersTab 6–6LibraryInfo 6–7SavingaComponent 6–7EditingaComponent 6–8SoftwareAssignments 6–8ComponentParameterization 6–8Chapter7.ComponentInterfaceTclReferenceInformationinaHardwareComponentDescriptionFile 7–1ComponentPhases 7–2WritingaHardwareComponentDescriptionFile 7–2ProvidingBasicInformation 7–3DeclaringParameters 7–3DeclaringInterfaces 7–5AddingFilesandGuidingGeneration 7–5SOPCBuilderUserGuideDecember2010AlteraCorporationContentsiiiDefaultBehaviors 7–6ValidationPhaseBehavior 7–6ElaborationPhaseBehavior 7–6GenerationPhaseBehavior 7–7EditPhaseBehavior 7–7ContentsiiiDefaultBehaviors 7–6ValidationPhaseBehavior 7–6ElaborationPhaseBehavior 7–6GenerationPhaseBehavior 7–7EditPhaseBehavior 7–7OverridingDefaultBehaviors 7–8ValidationCallback 7–9ElaborationCallback 7–9GenerationCallback 7–10EditorCallback 7–11HardwareTcldReference 7–12ModuleDefinition 7–14Parameters 7–21DisplayItems 7–29InterfacesandPorts 7–32Generation 7–38DeprecateddsandProperties 7–40Chapter8.ArchivingSOPCBuilderProjectsLimitations 8–1RequiredFiles 8–2Chapter9.SOPCBuilderMemorySubsystemDevelopmentWalkthroughExampleDesign 9–1ExampleDesignStartingPoint 9–3HardwareandSoftwareRequirements 9–3DesignFlow 9–4Component-LevelDesigninSOPCBuilder 9–4SOPCBuilderSystem-LevelDesign 9–4Simulation 9–5QuartusIIProject-LevelDesign 9–5Board-LevelDesign 9–5SimulationConsiderations 9–5On-ChipRAMandROM 9–6Component-LevelDesignforOn-ChipMemory 9–6SOPCBuilderSystem-LevelDesignforOn-ChipMemory 9–8SimulationforOn-ChipMemory 9–8QuartusIIProject-LevelDesignforOn-ChipMemory 9–8Board-LevelDesignforOn-ChipMemory 9–8ExampleDesignwithOn-ChipMemory 9–8EPCSSerialConfigurationDevice 9–9Component-LevelDesignforanEPCSDevice 9–9SOPCBuilderSystem-LevelDesignforanEPCSDevice 9–9SimulationforanEPCSDevice 9–9QuartusIIProject-LevelDesignforanEPCSDevice 9–10Board-LevelDesignforanEPCSDevice 9–10ExampleDesignwithanEPCSDevice 9–10SDRSDRAM 9–11Component-LevelDesignforSDRAM 9–11SOPCBuilderSystem-LevelDesignforSDRAM 9–11SimulationforSDRAM 9–11QuartusIIProject-LevelDesignforSDRAM 9–12Board-LevelDesignforSDRAM 9–12SOPCBuilderUserGuideivContentsExampleDesignwithSDRSDRAM 9–12DDRSDRAM 9–14DDR2SDRAM 9–14Off-ChipSRAMandFlashMemory 9–15Component-LevelDesignforSRAMivContentsExampleDesignwithSDRSDRAM 9–12DDRSDRAM 9–14DDR2SDRAM 9–14Off-ChipSRAMandFlashMemory 9–15Component-LevelDesignforSRAMandFlashMemory 9–15SOPCBuilderSystem-LevelDesignforSRAMandFlashMemory 9–17SimulationforSRAMandFlashMemory 9–17QuartusIIProject-LevelDesignforSRAMandFlashMemory 9–18Board-LevelDesignforSRAMandFlashMemory 9–18ExampleDesignwithSRAMandFlashMemory 9–20Chapter10.SOPCBuilderComponentDevelopmentWalkthroughSOPCBuilderComponentsandtheComponentEditor 10–1Prerequisites 10–1HardwareandSoftwareRequirements 10–2ComponentDevelopmentFlow 10–2TypicalDesignSteps 10–2HardwareDesign 10–3DesignExample:ChecksumHardwareAccelerator 10–4SoftwareDesign 10–6VerifyingtheComponent 10–6SharingComponents 10–7SystemInformationFiles(.sopcinfo) 10–7Chapter11.AvalonMemory-MappedBridgesStructureofaBridge 11–2ReasonsforUsingaBridge 11–2AddressMap forSystemswithAvalon-MMBridges 11–6Avalon-MMPipelineBridge 11–8ComponentOverview 11–9FunctionalDescription 11–10ClockCrossingBridge 11–12ChoosingClockCrossingMethodology 11–13FunctionalDescription 11–13Inst atingtheAvalon-MMClock-CrossingBridgeinSOPCBuilder 11–17ClockDomainCrossingLogic 11–17DescriptionofClockDomainAdapter 11–18LocationofClockDomainAdapter 11–19DurationofTransfersCrossingClockDomains 11–19ImplementingMultipleClockDomainsinSOPCBuilder 11–20Avalon-MMDDRMemoryHalf-RateBridge 11–20ResourceUsageandPerformance 11–21FunctionalDescription 11–22Inst atingtheCoreinSOPCBuilder 11–23ExampleSystem 11–24DeviceSupport 11–25HardwareSimulationConsiderations 11–25SoftwareProgramM.....................11–25Chapter12.AvalonStreaInterconnectComponentsInterconnectComponentUsage 12–1AddressMap........................12–2Adapter 12–2SOPCBuilderUserGuideDecember2010AlteraCorporationContentsvResourceUsageandPerformance 12–4Inst atingtheAdapterinSOPCBuilder 12–4DataFormatAdapter 12–5ResourceUsageandPerformance 12–6ContentsvResourceUsageandPerformance 12–4Inst atingtheAdapterinSOPCBuilder 12–4DataFormatAdapter 12–5ResourceUsageandPerformance 12–6Inst atingtheDataFormatAdapterinSOPCBuilder 12–6ChannelAdapter 12–7ResourceUsageandPerformance 12–8Inst atingtheChannelAdapterinSOPCBuilder 12–8ErrorAdapter 12–9Inst atingtheErrorAdapterinSOPCBuilder 12–9InstallationandLicensing 12–10HardwareSimulationConsiderations 12–10SoftwareProgramM.....................12–10AdditionalInformationDocumentRevisionHistory...................HowtoContactAltera..........................TypographicConventions.................Info–1Info–1SOPCBuilderUserGuideviContentsSOPCBuilderUserGuideDecemberviContentsSOPCBuilderUserGuideDecember2010AlteraCorporation1.IntroductiontoSOPCBuilderSOPCBuilderisapowerfulsystemdevelopmenttool.SOPCBuilderenablesyoutodefine1.IntroductiontoSOPCBuilderSOPCBuilderisapowerfulsystemdevelopmenttool.SOPCBuilderenablesyoutodefineandgenerateacompletesystem-on-a-programmable-chip(SOPC)inmuchlesstimethanusingtraditional,manualintegrationmethods.SOPCBuilderisincludedaspartoftheQuartusIIsoftware.ForaquickintroductiononhowtouseSOPCBuilder,followthesegeneralsteps:InstalltheQuartus®IIsoftware,whichincludesSOPCBuilder.Thisisavailableat.Takeadvantageoftheone-houronlinecourse,UsingSOPCBuilder.DownloadandrunthechecksumsampledesigndescribedinChapter9,SOPCBuilderMemorySubsystemDevelopmentWalkthrough.YoumayhaveusedSOPCBuildertocreatesystemsbasedontheNios®IIprocessor.However,SOPCBuilderismorethanaNiosIIsystembuilder;itisageneral-purposetoolforcreatingsystemsthatmayormaynotcontainaprocessorandmayincludeasoftprocessorotherthantheNiosIIprocessor.SOPCBuilderautomatesthetaskofintegratinghardwarecomponents.Usingtraditionaldesignmethods,youmustmanuallywriteHDLmodulestowiretogetherthepiecesofthesystem.UsingSOPCBuilder,youspecifythesystemcomponentsinaGUIandSOPCBuildergeneratestheinterconnectlogicautomatically.SOPCBuildergeneratesHDLfilesthatdefineallcomponentsofthesystem,andatop-levelHDLfilethatconnectsallthecomponentstogether.SOPCBuildergenerateseitherVerilogHDLorVHDLequally.Inadditiontoitsroleasasystemgenerationtool,SOPCBuilderprovidesfeaturestoeasewritingsoftwareandtoacceleratesystemsimulation.Thischapterincludesthefollowingsections:“ArchitectureofSOPCBuilderSystems”onpage1–1“FunctionsofSOPCBuilder”onpage1–5“OperatingSystemSupport”onpage1–8“TalkbackSupport”onpage1–8ArchitectureofSOPCBuilderSystemsAnSOPCBuildercomponentisadesignmodulethatSOPCBuilderrecognizesandcanautomaticallyintegrateintoasystem.Youcanalsodefineandaddcustomcomponentsorselectfromalistofprovidedcomponents.SOPCBuilderconnectsmultiplemodulestogethertocreateatop-levelHDLfilecalledtheSOPCBuildersystem.SOPCBuildergeneratessysteminterconnectfabricthatcontainslogictomanagetheconnectivityofallmodulesinthesystem.SOPCBuilderUserGuideChapter1:IntroductiontoSOPCBuilderArchitectureofSOPCBuilderSystemsSOPCBuilderModules1Chapter1:IntroductiontoSOPCBuilderArchitectureofSOPCBuilderSystemsSOPCBuilderModules1Thisdocumentreferstocomponentsastheclassdefinitionforamodule,forexampleaNios®IIprocessor.Aninstanceisaparameterizationofacomponentthat'sbeenaddedtoasystem,forexamplecpu_0.SOPCBuildermodulesarethebuildingblocksforcreatinganSOPCBuildersystem.SOPCBuildermodulesuseAvalon®interfaces,suchasmemory-mapped,strea andIRQ,forthephysicalconnectionofcomponents.YoucanuseSOPCBuildertoconnectanylogicaldevice(eitheron-chiporoff-chip)thathasanAvaloninterface.TherearedifferenttypesofAvaloninterfaces,asdescribedintheAvalonInterfaceSpecifications.fForsontheAvalon-MMinterfacerefertoChapter2,SystemInterconnectFabricforMemory-MappedInterfaces.ForsontheAvalon-STinterface,refertoChapter3,SystemInterconnectFabricforStreaInterfaces.ForsabouttheAvalon-STinterfaceprotocol,refertoAvalonInterfaceSpecifications.SOPCBuilderUserGuideDecember2010AlteraCorporationChapter1:IntroductiontoSOPCBuilderArchitectureofSOPCBuilderSystemsExampleSystemFigure1–1showsanFPGAdesignthatincludesanSOPCBuildersystemandcustomlogicmodules.YoucanintegratecustomlogicinsideoroutsidetheSOPCBuildersystem.Inthisexample,thecustomcomponentinsidetheSOPCBuildersystemcommunicateswithothermodulesthroughanAvalon-MMmasterinterface.ThecustomlogicoutsideoftheSOPCBuildersystemisconnectedtotheSOPCBuildersystemthroughaPIOinterface.TheSOPCBuildersystemincludestwoSOPCBuildercomponentswithAvalon-STsourceandsinkinterfaces.ThesysteminterconnectfabricconnectsalloftheSOPCBuildercomponentsusingtheAvalon-MMorsysteminterconneappropriate.Figure1–1.ExampleofanFPGAwithaSOPCBuilderSystemGeneratedbySOPCBuilderPrintedCircuitChapter1:IntroductiontoSOPCBuilderArchitectureofSOPCBuilderSystemsExampleSystemFigure1–1showsanFPGAdesignthatincludesanSOPCBuildersystemandcustomlogicmodules.YoucanintegratecustomlogicinsideoroutsidetheSOPCBuildersystem.Inthisexample,thecustomcomponentinsidetheSOPCBuildersystemcommunicateswithothermodulesthroughanAvalon-MMmasterinterface.ThecustomlogicoutsideoftheSOPCBuildersystemisconnectedtotheSOPCBuildersystemthroughaPIOinterface.TheSOPCBuildersystemincludestwoSOPCBuildercomponentswithAvalon-STsourceandsinkinterfaces.ThesysteminterconnectfabricconnectsalloftheSOPCBuildercomponentsusingtheAvalon-MMorsysteminterconneappropriate.Figure1–1.ExampleofanFPGAwithaSOPCBuilderSystemGeneratedbySOPCBuilderPrintedCircuitBoardFPGASystemModuleSystemInterconnectFabricPIO(8-bitDDR2MemoryStreaDataslave)ControllerSourceAvalon-MMMasterPortAvalon-MMSlavePortAvalon-STSourcePortAvalon-STSinkPortSOPCBuilderUserGuideSMDDR22MemoryDDR2MemoryBusBridgeCo-ProcessorStreaDataSinkProcessor(32-bitMaster)CustomComponentCustomLogicChapter1:IntroductiontoSOPCBuilderArchitectureofSOPCBuilderSystemsAcomponentcanbealogicaldevicethatisentirelycontainedwithintheSOPCBuildersystem,suchastheprocessorcomponentshowninFigureChapter1:IntroductiontoSOPCBuilderArchitectureofSOPCBuilderSystemsAcomponentcanbealogicaldevicethatisentirelycontainedwithintheSOPCBuildersystem,suchastheprocessorcomponentshowninFigure1–1.Alternately,acomponentcanaaninterfacetoanoff-chipdevice,suchastheDDR2interfacecomponentinFigure1–1.InadditiontotheAvaloninterface,acomponentcanhaveothersignalsthatconnecttologicoutsidetheSOPCBuildersystem.Non-Avalonsignalscanprovideaspecial-purposeinterfacetotheSOPCBuildersystem,suchasthePIOinFigure1–1.Thesenon-AvalonsignalsaredescribedinConduitInterfacechapterintheAvalonInterfaceSpecifications.Alteraandthird-partydevelopersprovideincluding:y-to-useSOPCBuildercomponents,Microprocessors,suchastheNiosIIprocessorMicrocontrollerperipherals,suchasaScatter-GatherDMAControllerandtimerSerialcommunicationinterfaces,suchasaUARTandaserialperipheralinterface(SPI)GeneralpurposeI/OCommunicationsperipherals,suchasa10/100/1000EthernetMACInterfacestooff-chipdevicesCustomComponentsYoucanimportHDLmodulesandentitiesthatyouwriteusingVerilogHDLorVHDLintoSOPCbuilderascustomcomponents.YouusethefollowingdesignflowtointegratecustomlogicintoanSOPCBuildersystem:1.2.3.Determinetheinterfacesusedtointeractwithyourcustomcomponent.CreatethecomponentlogicusingeitherVerilogHDLorVHDL.UsetheSOPCBuildercomponenteditortocreateanSOPCBuildercomponentwithyourHDLfiles.4.Instateyourcomponentinthesystem.OnceyouhavecreatedanSOPCBuildercomponent,youcanusethecomponentinotherSOPCBuildersystems,andsharethecomponentwithotherdesignteams.fForinstructionsondeveloacustomSOPCBuildercomponent,thesaboutthefilestructureofacomponent,orthecomponenteditor,refertoChapter4,SOPCBuilderComponents.fForsontheAvalon-MMinterfacerefertoChapter2,SystemInterconnectFabricforMemory-MappedInterfaces.ForsontheAvalon-STinterface,refertoChapter3,SystemInterconnectFabricforStreaInterfaces.SOPCBuilderUserGuideDecember2010AlteraCorporationChapter1:IntroductiontoSOPCBuilderFunctionsofSOPCBuilderYoucanalsouseSOPC-ycomponentsthatweredevelopedbythird-parties.AlteraawardstheSOPCBuilderyChapter1:IntroductiontoSOPCBuilderFunctionsofSOPCBuilderYoucanalsouseSOPC-ycomponentsthatweredevelopedbythird-parties.AlteraawardstheSOPCBuilderycertificationtoIPfunctionsthatareytointegratewiththeNiosIIembeddedprocessororthesysteminterconnectfabricviaSOPCBuilder.ThesecoressupporttheAvalon-MMinterfaceortheAvalonStrea(Avalon-ST)interfaceandmayincludeconstraints,softwaredrivers,simulationms,andreferencedesignswhenapplicable.TofindSOPCBuilderythird-partycomponentsthatyoucanpurchaseanduseinSOPCBuildersystems,completethefollowingsteps:1.2.OntheToolsinSOPCBuilder,clickDownloadComponents.yrinOntheIntellectualPropertySolutionswge,typeSOPCBuildertheboxlabeledSearchforIP,DevelopmentKitsandReferenceDesigns.FunctionsofSOPCBuilderThissectiondescribesthefunctionsofSOPCBuilder.DefiningandGeneratingtheSystemHardwareSOPCBuilderallowsyoutodesignthestructureofahardwaresystem.TheGUIallowsyoutoaddcomponentstoasystem,configurethecomponents,andspecifyconnectivity.Afteryouaddandparameterizecomponents,SOPCBuildergeneratesthesysteminterconnectfabric,andoutputsHDLfilestoyourprojectdirectory.Duringsystemgeneration,SOPCBuildercreatesthefollowingitems:AnHDLfileforthetop-levelSOPCBuildersystemandforeachcomponentinthe<system_name>.vforVerilogHDLdesignsand<system_name>.vhdforVHDLdesigns.■SynopsisDesignConstraintsfile(.sdc)foranalysis.■ABlockSymbolFile(.bsf)representationofthetop-levelSOPCBuildersystemforuseinQuartusIIBlockDiagramFiles(.bdf).Anexampleofaninstanceofthetop-levelHDLfile,<SOPC_project_name_inst>.v■■or<SOPC_project_name_inst>.vhd,whichdemonstrateshowtoinsttop-levelHDLfileinyourcode.atetheAdatasheetcalled<system_name>.htmlthatprovidesasystemoverviewincludingthefollowinginformation:AllexternalconnectionsforthesystemAmemorymapshowingtheaddressofeachAvalon-MMslavewithrespecttoeachAvalon-MMmastertowhichitisconnectedAllparameterassignmentsforeachcomponent■AfunctionaltestbenchfortheSOPCBuildersystemandMprojectfilesSim®simulation■SOPCBuilderUserGuideChapter1:IntroductiontoSOPCBuilderSOPCBuilderDesignFlowSOPCinformationfile(.sopcinfo)thatdescribesallofthecomponentsandconnectionsinyoursystem.Thisfileisacompletesystemdescription,andisusedbydownstreamtoolssuchastheNiosIItoolchain.ItalsodescribestheChapter1:IntroductiontoSOPCBuilderSOPCBuilderDesignFlowSOPCinformationfile(.sopcinfo)thatdescribesallofthecomponentsandconnectionsinyoursystem.Thisfileisacompletesystemdescription,andisusedbydownstreamtoolssuchastheNiosIItoolchain.Italsodescribestheparameterizationofeachcomponentinthesystem;consequently,youcanparseits■contentstogetrequirementswhendevelocomponents.softwaredriversforSOPCBuilderAQuartusIIIPFile(.qip)thatprovidestheQuartusIIsoftwarewithallrequiredinformationaboutyourSOPCBuildersystem.The.qipfileincludesreferencestothefollowinginformation:HDLfilesusedintheSOPCBuildersystem■AnalyzerSynopsysDesignConstraint(.sdc)filesComponentdefinitionfilesforarchivingpurposesAfteryougeneratetheSOPCBuildersystem,youcancompileitwiththeQuartusIIsoftware,oryoucaninstateitinalargerFPGAdesign.CreatingaMemoryMapforSoftwareDevelopmentWhenyourSOPCBuildersystemincludesaNiosIIprocessor,SOPCBuildergeneratesaheaderfile,cpu.h,thatprovidesthebaseaddressofeachAvalon-MMslavecomponent.Inaddition,eachslavecomponentcanprovidesoftwaredriversandothersoftwarefunctionsandlibrariesfortheprocessor.YoucancreateCheaderfilesforyoursystemusingthesopc-create-header-filesutility.ffForstypesopc-create-header-files--helpinaNiosIIdshell.FormoretotheDevelosabouthowtoprovideNiosIIsoftwaredriversforcomponents,referDeviceDriversfortheHardwareAbstractionLayerchapteroftheNiosIISoftwareDeveloper’sHandbook.TheNiosIIEDSisseparatefromSOPCBuilder,butitusestheoutputofSOPCBuilderasthefoundationforsoftwaredevelopment.CreatingaSimulationMBenchYoucansimulateyoursystemaftergeneratingitwithSOPCBuilder.Duringsystemgeneration,SOPCBuilderoutputsasimulationtestbenchandaMSimsetupscriptthateasesthesystemsimulationeffort.Thetestbenchdoesthefollowing:InstatestheSOPCBuildersystemDrivesallclocksandresetsInstatessimulationmsforoff-chipdeviceswhenavailableSOPCBuilderDesignFlowFigure1–2illustratesanexamplebottom-updesignflowinSOPCBuilderwhichstartswithcomponentdesign.Asthisflowdiagramillustrates,thetypicaldesignflowincludesthefollowinghigh-levelsteps:1.PackageyourcomponentforSOPCBuilderusingtheComponentEditor.SOPCBuilderUserGuideDecember2010AlteraCorporationChapter1:IntroductiontoSOPCBuilderSOPCBuilderDesignFlow2.Simulateattheunit-level,possiblyincorporatingAvalonBFMstoverifythesystem.CompletetheSOPCBuilderdesignbyaddingothercomponents,specifyinginterrupts,clocks,resets,andaddresses.GeneratetheChapter1:IntroductiontoSOPCBuilderSOPCBuilderDesignFlow2.Simulateattheunit-level,possiblyincorporatingAvalonBFMstoverifythesystem.CompletetheSOPCBuilderdesignbyaddingothercomponents,specifyinginterrupts,clocks,resets,andaddresses.GeneratetheSOPCBuildersystem.Performsystemlevelsimulation.Constrainandcompilethedesign.DownloadthedesigntoanAlteradevice.Testinhardware..7.8.Figure1–2.CompleteQsysDesignFlow12DoesYesNo38Yes569DoesYesNo10SOPCBuilderUserGuide7DoesNoSimulationSystem4Chapter1:IntroductiontoSOPCBuilderVisualizationofSOPCBuilderSystems1Inthealternativetop-downvaliddesignflow,youbeginbydesigningtheSOPCChapter1:IntroductiontoSOPCBuilderVisualizationofSOPCBuilderSystems1Inthealternativetop-downvaliddesignflow,youbeginbydesigningtheSOPCBuildersystemandthendefineandinstatecustomSOPCBuilddercomponent.Thisapproachclarifiesthesystemrequirementsearlierinthedesignprocess.Designstargetingdevicesarerequirespecificdesignconstraints.Consequently,ifyouaretargetingaseriesdevice,youmustverifyyoudesignforthecompaniondevice.Followtheseguidelinestoverifyyourdesignforbothdevices:1.IntheQuartusIIDevicedialogbox,selectboththeFPGAandtheappropriatecompaniondevice.InStep8ofthedesignflowshowninFigure1–2,compileforboththeFPGAanddevice.2.3.AfterStep10ofthedesignflowshowninFigure1–2,ifFPGsimulationandhardwareverificationtests,generatethesesallfunctionalhandoffarchiveandsendthisarchivetotheandtapeout.DesignCenterforthebackendflowVisualizationofSOPCBuilderSystemsYoucanusetheFiltersdialogboxtocustomizethedisplayofyoursysteminthepanel.Youcanfilterthedisplayofyoursystembyinterfacetype,instancename,interfacetype,orusingcustomtags.Forexample,youcanusefilteringtoviewonlyinstancesthatincludeanAvalon-MMinterfaceorinstancesthatareconnectedtoaparticularNiosIIprocessor.Formoreinformation,refertoQuartusIIonlineHelp.OperatingSystemSupportSOPCBuildersupportsalloftheoperatingsystemsthattheQuartusIIsoftwaresupports.fForsoninstallationandlicensing,refertotheAlteraSoftwareInstallationandLicensingManual.TalkbackSupportTalkbackisaQuartusIIsoftwarefeaturethatprovidesfeedbacktoAlteraontoolandIPfeatureusage.Alterausesthedatatohelpguidefutureproductplanningefforts.TalkbacksendsAlterainformationontheAlteracomponentsyouuse,including:interfacetypes,interfaceproperties,parameternamesandvalues,clocking,andsoftwareassignments.ForcomponentsfromAltera,Talkbacksendsthecomponentparametervaluestohelpunderstandwhatfeaturesofthecomponentarebeingused.Fornon-Alteracomponents,TalkbackcollectsinformationabouthowinterfacessuchasAvalon-MMarebeingused.Connectivitybetweencomponentsisnot.TheTalkbackfiledoesnotincludeinformationaboutsystemconnectivity,interrupts,orthememorymapseenbyeachmasterinthesystem.Talkbackcollectsthesameverygeneralinformationaboutyourproprietarycomponents.TheTalkbackfeatureisenabledbydefault.YoucandisableTalkbackfromwithintheQuartusIIsoftwareifyoudonotwishtoshareyourusagedatawithAltera.SOPCBuilderUserGuideDecember2010AlteraCorporation2.SystemInterconnectFabricforMemory-MappedInterfacesThesysteminterconnectfabricformemory-mappedinterfacesisahigh-bandwidth2.SystemInterconnectFabricforMemory-MappedInterfacesThesysteminterconnectfabricformemory-mappedinterfacesisahigh-bandwidthinterconnectstructureforconnectingcomponentsthatusetheAvalon®Memory-Mapped(Avalon-MM)interface.Thesysteminterconnectfabricconsumeslesslogic,providesgreaterflexibility,andhigherthroughputthanatypicalsharedsystembus.Itisacross-connectfabricandnotatristatedortimedomainmultiplexedbus.Thischapterdescribesthefunctionsofsysteminterconnectfabricformemory-mappedinterfacesandtheimplementationofthosefunctions.High-LevelDescriptionThesysteminterconnectfabricisthecollectionofinterconnectandlogicresourcesthatconnectsAvalon-MMmasterandslavesoncomponentsinasystem.SOPCBuildergeneratesthesysteminterconnectfabrictomatchtheneedsofthecomponentsinasystem.Thesysteminterconnectfabricimplementstheconnectionsofasystem.Itguaranteesthatsignalsareroutedcorrectlybetweenmasterandslaves,aslongastheportsadheretotherulesoftheAvalonInterfaceSpecifications.Thischapterprovidesinformationonthefollowingtopics:“AddressDecoding”onpage2–3“DatapathMultiplexing”onpage2–4“WaitStateInsertion”onpage2–5■■■“PipelinedTransfers”onpage2–6■“DynamicBusSizingandNativeAddressAlignment”onpage2–6“ArbitrationforMultimasterSystems”onpage2–9“BurstAdapters”onpage2–14“Interrupts”onpage2–15“ResetDistribution”onpage2–16■■■■■fForsabouttheAvalon-MMinterface,refertotheAvalonInterfaceSpecifications.Systeminterconnectfabricformemory-mappedinterfacessupportsthefollowingitems:Anynumberofmasterandslavecomponents.Themaster-to-slaverelationshipcanbeone-to-one,one-to-many,many-to-one,ormany-to-many.On-chipcomponents.Interfacestooff-chipdevices.Masterandslavesofdifferentdatawidths.Componentsoperatingindifferentclockdomains.ComponentsusingmultipleAvalon-MMports.SOPCBuilderUserGuideChapter2:SystemInterconnectFabricforMemory-MappedInterfacesHigh-LevelDescriptionFigure2–1showsasimplifieddiagramofthesysteminterconnectfabricinanexamplememory-mappedsystemwithmultiplemasters.1 Allfiguresinthischapteraresimplifiedtoshowonlytheparticularfunctionbeingdiscussed.Inacompletesystem,thesysteminterconnectfabricmightaltertheaddress,data,andcontrolpathsbeyondwhatisshowninanyoneparticularfigure.Figure2–1.SystemInterconnectFabric—ExampleSystemSProcessorControlDMAControllerWriteDataMMMMMUXSystemInterconnectFabricArbiterArbiterTri-StateBridgeSSSInstructionMemoryDataMemorySDRAMControllerWriteData&ControlSigna