习题答案公务员考试资格考试认证教育专区

EDA技术与VHDL

(第二版)习题解答第一页，共21页。process(s0,s1,a,b,c,d)beginifs0='0'ands1='0'theny<=a;elsifs0='1'ands1='0'theny<=b;elsifs0='0'ands1='1'theny<=c;elsey<=d;endif;endprocess;用IF_THEN语句：第二页，共21页。architecturehdlarchofmux41issignalstmp:std_logic_vector(1downto0);Beginstmp<=s1&s0;process(s0,s1,a,b,c,d)begincasestmpiswhen"00"=>y<=a;when"01"=>y<=b;when"10"=>y<=c;whenothers=>y<=d;endcase;endprocess;使用CASE语句：第三页，共21页。3-3.

图3-18所示的是双2选1多路选择器构成的电路MUXK，对于其中MUX21A，当s='0'和'1'时，分别有y<='a'和y<='b'。试在一个结构体中用两个进程来表达此电路，每个进程中用CASE语句描述一个2选1多路选择器MUX21A。

图3-18双2选1多路选择器

参考答案第四页，共21页。Libraryieee;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYVOTEISPORT(a1,a2,a3,s0,s1:INSTD_LOGIC;

outy:

out

std_logic);ENDVOTE;architecturehdlarchofMUXKissignaltmp:std_logic;beginprocess(s0,a2,a3)beginifs0='0'thentmp<=a2;elsetmp<=a3;endif;endprocess;process(s1,a1,tmp)beginifs1='0'thenouty<=a1;elseouty<=tmp;endif;endprocess;endhdlarch;第五页，共21页。3-4.

给出1位全减器的VHDL描述。要求：

(1)首先设计1位半减器，然后用例化语句将它们连接起来，图3-20中h_suber是半减器，diff是输出差，s_out是借位输出，sub_in是借位输入。

(2)以1位全减器为基本硬件，构成串行借位的8位减法器，要求用例化语句来完成此项设计(减法运算是

x–y-sun_in=diffr)。

图3-321位全减器

t0t1t2第六页，共21页。libraryieee;useieee.std_logic_1164.all;entityh_suberisport(x,y:instd_logic;diff,s_out:outstd_logic);endentity;architecturehdlarchofh_suberisbeginprocess(x,y)begindiff<=xxory;s_out<=(notx)andy;endprocess;endhdlarch;1位半减器：第七页，共21页。LIBRARYieee;USEieee.std_logic_1164.all;ENTITYsuberIS--1位全减器port(x,y:INSTD_LOGIC;sub_in:INSTD_LOGIC;diffr:OUTSTD_LOGIC;sub_out:OUTSTD_LOGIC);ENDsuber;ARCHITECTUREscharchOFsuberIScomponenth_suberPORT(x,y:INSTD_LOGIC;diff,s_out:OUTSTD_LOGIC);endcomponent;signalt0,t1,t2:STD_LOGIC;BEGINu1:h_suberPORTMAP(x=>x,y=>y,diff=>t0,s_out=>t1);u2:h_suberPORTMAP(x=>t0,y=>sub_in,diff=>diffr,s_out=>t2);sub_out<=t1ORt2;END;第八页，共21页。LIBRARYieee;USEieee.std_logic_1164.all;ENTITYsub8ISport(a，b:INstd_logic_vector(7downto0);sin:INSTD_LOGIC;sout:OUTSTD_LOGIC;c:OUTstd_logic_vector(7downto0));ENDsub8;ARCHITECTUREhdlarchOFsub8IScomponentsuberPORT(x:INSTD_LOGIC;y:INSTD_LOGIC;sub_in:INSTD_LOGIC;diffr:OUTSTD_LOGIC;sub_out:OUTSTD_LOGIC);endcomponent;signalstmp:std_logic_vector(8downto0);BEGINstmp(0)<=sin;sout<=stmp(8);gensub:foriin0to7generateu1:suberPORTMAP(x=>a(i),y=>b(i),sub_in=>stmp(i),diffr=>c(i),sub_out=>stmp(i+1));endgenerate;end；第九页，共21页。3-5.图3-33是一个含有上升沿触发的D触发器的时序电路，试写出此电路的VHDL设计文件。

图3-19时序电路图

第十页，共21页。libraryieee;useieee.std_logic_1164.all;entityDFF1isport(CL,CLK0:instd_logic;out1:outstd_logic);endentity;ArchitecturehdlarchofDFF1issignaltmp:std_logic;beginprocess(CLK0)beginifrising_edge(CLK0)thentmp<=not(tmporCL);endif;endprocess;out1<=nottmp;endhdlarch;第十一页，共21页。3-6.

根据图3-34，写出顶层文件MX3256.VHD的VHDL设计文件。图3-34题3-6电路图

第十二页，共21页。LIBRARYieee;USEieee.std_logic_1164.all;ENTITYMX3256ISport(INA,INB,INCK,INC:INSTD_LOGIC;E,OUT1:OUTSTD_LOGIC);ENDMX3256;ARCHITECTUREschtypeOFMX3256IScomponentLK35PORT(A1:INSTD_LOGIC;A2:INSTD_LOGIC;CLK:INSTD_LOGIC;Q1:OUTSTD_LOGIC;Q2:OUTSTD_LOGIC);endcomponent;signalt1,t2,t3,t4:STD_LOGIC;BEGINU1:LK35PORTMAP(A1=>INA,A2=>INB,CLK=>INCK,Q1=>t3,Q2=>t2);U2:LK35PORTMAP(A1=>t2,A2=>t1,CLK=>INCK,Q1=>t4,Q2=>OUT1);process(INCK,INC)beginif(INC='0')thent1<='0';elsif(rising_edge(INCK))thent1<=t2;endif;endprocess;e<=t4whent2='0'elset3;END;第十三页，共21页。LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_unsigned.all;USEieee.std_logic_arith.all;ENTITYex6_10ISport(sck:instd_logic;sda:instd_logic;q:outstd_logic_vector(7downto0));END;ARCHITECTUREhdlarchOFex6_10ISsignalshift:std_logic_vector(7downto0);BEGINprocess(sck)beginif(rising_edge(sck))thenshift<=sda&shift(7downto1);endif;endprocess;q<=shift;END;第十四页，共21页。4-8用原理图输入方式设计一个7人表决电路，参加表决者7人，同意为1，不同意为0，同意者过半则表决通过，绿指示灯亮；表决不通过则红指示灯亮。第十五页，共21页。Libraryieee;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYVOTEISPORT(DIN:INSTD_LOGIC_VECTOR(6DOWNTO0);

RED,GREEN:

out

std_logic);ENDVOTE;ArchitectureONEOFVOTEISSignaltemp:STD_LOGIC_VECTOR(2DOWNTO0);BEGINU1:PROCESS(DIN)VARIABLEQ:STD_LOGIC_VECTOR(2DOWNTO0);BEGINQ:=“000”;FORnIN0TO6LOOPIF(DIN(n)=‘1’)thenQ:=Q+1;endif;endloop;temp<=Q;EndprocessU1;U2:

Process(temp)

Begin

if

temp>=“100”then

Green<='1';

Red<='0';

else

Green<='0';

Red<='1';

endif;

EndProcessU2;EndArchitectureONE;第十六页，共21页。4-9基于原理图输入方式，用D触发器构成按循环码(000->001->011->111->101->100->000)规律工作的六进制同步计数器。第十七页，共21页。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYs_machineISPORT(clk:INSTD_LOGIC;outputs:OUTSTD_LOGIC(2downto0));ENDs_machine;ARCHITECTUREbehvOFs_machineISTYPEFSM_STIS(s0,s1,s2,s3,s4,s5);

SIGNALcurrent_state,next_state:FSM_STBEGINREG:PROCESS(clk)--主控时序进程

BEGINIFclk='1'ANDclk'EVENTTHENcurrent_state<=next_state;ENDIF;EN