FPGA技术课程作业

FPGA技术课程作业FPGA技术课程作业FPGA技术课程作业FPGA技术课程作业编制仅供参考审核批准生效日期地址：电话：传真:邮编:1.分析程序,完成下列各题：1）完成程序填空。2）画出该代码综合后的电路图。moduletest2(clk,reset,in1,in2,in3,out1,out2);inputclk,reset;inputin1,in2,in3;outputout1,out2;regout1,out2;integertemp1,temp2;always@(posedgeclkorposedgereset)if(reset) begin temp1<=0; temp2<=0; end elsebegin temp1<=in1&in2; temp2<=in2|in3; end always@(posedgeclk) begin out1<=temp1&temp2; out2<=temp1^in3; endendmodule2、分析程序，完成下列题目：1）完成程序填空。2）根据图一所画出的输入激励波形，编写测试文件，仿真截图在0到900ns时间区间里输出端口的输出波形。moduletest1(data_1,data_2,data_3,data_out1,data_out2);inputdata_1,data_2,data_3;outputdata_out1,data_out2;taskwriteburst;inputa,b;integerc;c=a+b;endtaskregdata_out1,data_out2;always@(data_1ordata_2or3)beginwrite(data_1,data_2,data_out1);write(data_2,data_3,data_out2); endendmodule图一3.根据下面的VerilogHDL代码，画出综合后的电路图。moduletest12(out,clk,in1,in2,in3,in4);inputclk;inputin1,in2,in3,in4;outputout;regout;regtemp1,temp2;always@(posedgeclk)begintemp1<=in1&in2;temp2<=temp1|in3;out<=temp2|in4;endendmodule4.根据图1所示的原理图写出相应的VerilogHDL程序，其中DFF模块是上升沿触发的触发器，编写相应的测试程序，在ISE软件中完成仿真，对仿真波形图进行截图。图二程序：

modulemy_moduke(clk,xin,out);inputclk,xin;outputout;regout;regtemp;always@(posedgeclk)begintemp<=xin|out;endalways@(posedgeclk)beginout=temp;endendmodule激励文件：initial begin clk=0; forever#30clk=~clk; endinitialbegin 用VerilogHDL设计一个四分频电路，在ISE软件中完成仿真，对仿真波形图进行截图。1）输入信号：clk--------输入时钟reset--------同步复位信号，当reset=1’b1时，系统输出置零，当reset=1’b0时，系统正常工作。2）输出信号：clk_out--------输出信号，其频率是输入时钟的四分之一moduleD_4div(clkin,reset_n,clkout);inputclkin,reset_n;outputclkout;wirein1,in2,clkin_2;regout;regclkout_1;assignin1=~clkout_1;assignclkin_2=clkout_1;assignin2=~out;assignclkout=out;always@(posedgeclkin)计一个带有异步复位控制端和时钟使能控制端的10进制计数器。module

Counter(clk,clk_key,clr,ena,cout,sel,seg);input

clk,clk_key,clr,ena;output

cout;output

[7:0]sel,seg;assign

sel=8'hf0;wire

clk_k;debounce_module

U0

(.CLK(clk),.RSTn(clr),.Pin_In(clk_key),.Pin_Out(clk_k));wire

[3:0]sum;count

U1(.clk(clk),.clk_k(clk_k),.clr(clr),.ena(ena),.cout(cout),.sum(sum));tube

U2(.clk(clk),.sum(sum),.seg(seg));endmodule计数模块module

count(clk,clk_k,clr,ena,cout,sum);input

clk,clk_k,clr,ena;output

cout;output

[3:0]sum;reg

cout;reg

[3:0]sum;reg

a,b;always@(posedge

clk)begina<=clk_k；b<=a;endwire

key_posedge=(~b&a)

1'b1

:1'b0;always@(posedge

clk)beginif(clr)begincout

<=0；sum

<=0;endelse

if(key_posedge

&

ena) beginif(sum<4'd9) beginsum<=sum+1'b1;cout<=0;endelse

begincout<=1; sum<=0;endendelsebegincout<=cout；sum<=sum;endendendmodule数码管moduletube(clk,sum,seg);inputclk;input[3:0]sum;output[7:0]seg;reg[7:0]seg;always@(posedgeclk)begincase(sum) 4'd0:seg<=8'hc0;4'd1:seg<=8'hf9;4'd2:seg<=8'ha4;4'd3:seg<=8'hb0; 4'd4:seg<=8'h99;4'd5:seg<=8'h92;