超大CMOS集成电路原理chapter9

1、Digital Integrated CircuitsA Design PerspectiveCoping withInterconnectJan M. RabaeyAnantha ChandrakasanBorivoje NikolicDecember 15, 2002Impact of Interconnect Parasitics Reduce Robustness Affect Performance Increase delay Increase power dissipationClasses of Parasitics Capacitive Resistive Inductive

2、INTERCONNECTDealing with CapacitanceCapacitive Cross TalkCapacitive Cross TalkDynamic Node3 x 1 mm overlap: 0.19 V disturbance CYCXYVDDPDNCLKCLKIn1In2In3YX2.5 V0 VCapacitive Cross TalkDriven NodetXY = RY(CXY+CY)Keep time-constant smaller than rise timeV (Volt)00.50.450.40.35010.

3、80.6t (nsec)0.40.2XYVXRYCXYCYtrDealing with Capacitive Cross TalkAvoid floating nodesProtect sensitive nodesMake rise and fall times as large as possibleDifferential signalingDo not run wires together for a long distanceUse shielding wiresUse shielding layersShieldingGNDGNDShieldingwireSubstrate (GN

4、D)ShieldinglayerVDDCross Talk and PerformanceCc- When neighboring lines switch in opposite direction of victim line, delay increasesDELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRESMiller Effect - Both terminals of capacitor are switched in opposite directions (0 Vdd, Vdd 0) - Effective voltage is

5、doubled and additional charge is needed (from Q=CV)Impact of Cross Talk on Delay r is ratio between capacitance to GND and to neighborStructured Predictable InterconnectExample: Dense Wire Fabric (Sunil Kathri)Trade-off: Cross-coupling capacitance 40 x lower, 2% delay variation Increase in area and

6、overall capacitance Also: FPGAs, VPGAsInterconnect ProjectionsLow-k dielectricsBoth delay and power are reduced by dropping interconnect capacitanceTypes of low-k materials include: inorganic (SiO2), organic (Polyimides) and aerogels (ultra low-k)The numbers below are on the conservative side of the

7、 NRTS roadmapeEncoding Data Avoids Worst-CaseConditionsEncoderDecoderBusInOutDriving Large CapacitancesVinVoutCLVDD Transistor Sizing Cascaded BuffersUsing Cascaded BuffersCL = 20 pFInOut12N0.25 mm processCin = 2.5 fFtp0 = 30 psF = CL/Cin = 8000fopt = 3.6 N = 7tp = 0.76 ns(See Chapter 5)Output Drive

8、r DesignTrade off Performance for Area and EnergyGiven tpmax find N and fAreaEnergyDelay as a Function of F and N101357Number of buffer stages N91110,0001000100tp/tp0F= 100F=1000F=10,000tp/tp0Output Driver DesignTransistor Sizes for optimally-sized cascaded buffer tp = 0.76 nsTransistor Sizes of red

9、esigned cascaded buffer tp = 1.8 ns0.25 mm process, CL = 20 pFHow to Design Large TransistorsG(ate)S(ource)D(rain)MultipleContactssmall transistors in parallelReduces diffusion capacitanceReduces gate resistanceBonding Pad DesignBonding PadOutInVDDGND100 mmGNDOutESD ProtectionWhen a chip is connecte

10、d to a board, there is unknown (potentially large) static voltage differenceEqualizing potentials requires (large) charge flow through the padsDiodes sink this charge into the substrate need guard rings to pick it up.ESD ProtectionDiodeChip PackagingBond wires (25m) are used to connect the package t

11、o the chip Pads are arranged in a frame around the chip Pads are relatively large (100m in 0.25m technology),with large pitch (100m)Many chips areas are pad limitedPad FrameLayoutDie PhotoChip PackagingAn alternative is flip-chip:Pads are distributed around the chipThe soldering balls are placed on

12、padsThe chip is flipped onto the packageCan have many more padsTristate BuffersInEnEnVDDOutOut = In.En + Z.EnVDDInEnEnOutIncreased output driveReducing the swing Reducing the swing potentially yields linear reduction in delay Also results in reduction in power dissipation Delay penalty is paid by th

13、e receiver Requires use of “sense amplifier” to restore signal level Frequently designed differentially (e.g. LVDS)Single-Ended Static Driver and ReceiverCLVDDVDDVDDdriverreceiverVDDLVDDLInOutOutDynamic Reduced Swing NetworkfIn2.fIn1.fM2M1M3M4CbusCoutBusOutVDDVDDV(Volt)fVbusVasymVsym246time (ns)8101

14、200.511.522.50INTERCONNECTDealing with ResistanceImpact of ResistanceWe have already learned how to drive RC interconnectImpact of resistance is commonly seen in power supply distribution:IR dropVoltage variationsPower supply is distributed to minimize the IR drop and the change in current due to sw

15、itching of gatesRI Introduced NoiseM1XIR9RDVfpreDVVDDVDD2DV9IResistance and the Power Distribution ProblemSource: Cadence Requires fast and accurate peak current prediction Heavily influenced by packaging technologyBeforeAfterPower DistributionLow-level distribution is in Metal 1Power has to be stra

16、pped in higher layers of metal.The spacing is set by IR drop, electromigration, inductive effectsAlways use multiple contacts on strapsPower and Ground Distribution3 Metal Layer Approach (EV4)3rd “coarse and thick” metal layer added to thetechnology for EV4 designPower supplied from two sides of the

17、 die via 3rd metal layer2nd metal layer used to form power grid90% of 3rd metal layer used for power/clock routingMetal 3Metal 2Metal 1Courtesy Compaq4 Metal Layers Approach (EV5)4th “coarse and thick” metal layer added to thetechnology for EV5 designPower supplied from four sides of the dieGrid str

18、apping done all in coarse metal90% of 3rd and 4th metals used for power/clock routingMetal 3Metal 2Metal 1Metal 4Courtesy Compaq2 reference plane metal layers added to thetechnology for EV6 designSolid planes dedicated to Vdd/VssSignificantly lowers resistance of gridLowers on-chip inductance6 Metal

19、 Layer Approach EV6Metal 4Metal 2Metal 1RP2/VddRP1/VssMetal 3Courtesy CompaqElectromigration (1)Electromigration (2)Resistivity and PerformanceDiffused signal propagationDelay L2CN-1CNC2R1R2C1TrVinRN-1 RNThe distributed rc-lineThe Global Wire ProblemChallengesNo further improvements to be expected a

20、fter the introduction of Copper (superconducting, optical?)Design solutionsUse of fat wiresInsert repeaters but might become prohibitive (power, area)Efficient chip floorplanningTowards “communication-based” design How to deal with latency?Is synchronicity an absolute necessity?()outwwdoutdwwdCRCRCR

21、CRT+=693.0377.0Interconnect Projections: CopperCopper is planned in full sub-0.25 mm process flows and large-scale designs (IBM, Motorola, IEDM97)With cladding and other effects, Cu 2.2 mW-cm vs. 3.5 for Al(Cu) 40% reduction in resistanceElectromigration improvement; 100X longer lifetime (IBM, IEDM9

22、7)Electromigration is a limiting factor beyond 0.18 mm if Al is used (HP, IEDM95)ViasInterconnect:# of Wiring Layers# of metal layers is steadily increasing due to: Increasing die size and device count: we need more wires and longer wires to connect everything Rising need for a hierarchical wiring n

23、etwork; local wires with high density and global wires with low RC0.25 mm wiring stackDiagonal WiringyxdestinationManhattansourcediagonal 20+% Interconnect length reduction Clock speed Signal integrity Power integrity 15+% Smaller chips plus 30+% via reductionCourtesy Cadence X-initiativeUsing Bypas

24、sesDriverPolysilicon word linePolysilicon word lineMetal word lineMetal bypassDriving a word line from both sidesUsing a metal bypassWLWLKcellsReducing RC-delayRepeater(chapter 5)Repeater Insertion (Revisited)Taking the repeater loading into accountFor a given technology and a given interconnect lay

25、er, there exists an optimal length of the wire segments between repeaters. The delay of these wire segments is independent of the routing layer!INTERCONNECTDealing with InductanceL di/dtImpact of inductance on supply voltages: Change in current induces a change in voltage Longer supply lines have la

26、rger LCLVDDVDDLi(t)VoutVinGNDLL di/dt: Simulation00.511.52x 10-900.511.522.5Vout (V)00.511.52x 10-900.020.04iL (A)00.511.52x 10-900.51VL (V)time (nsec)00.511.52x 10-900.511.522.500.511.52x 10-900.020.0400.511.52x 10-900.51time (nsec)Input rise/fall time: 50 psecInput rise/fall time: 800 psecdecouple

27、dWithout inductorsWith inductorsDealing with Ldi/dtSeparate power pins for I/O pads and chip core.Multiple power and ground pins. Careful selection of the positions of the power and ground pins on the package.Increase the rise and fall times of the off-chip signals to the maximum extent allowable.Sc

28、hedule current-consuming transitions. Use advanced packaging technologies.Add decoupling capacitances on the board.Add decoupling capacitances on the chip.Choosing the Right PinDecoupling CapacitorsDecoupling capacitors are added: on the board (right under the supply pins) on the chip (under the sup

29、ply straps, near large buffers)De-coupling Capacitor RatiosEV4total effective switching capacitance = 12.5nF128nF of de-coupling capacitancede-coupling/switching capacitance 10 xEV513.9nF of switching capacitance 160nF of de-coupling capacitanceEV634nF of effective switching capacitance320nF of de-c

30、oupling capacitance - not enough!Source: B. Herrick (Compaq)EV6 De-coupling CapacitanceDesign for Idd= 25 A Vdd = 2.2 V, f = 600 MHz0.32-F of on-chip de-coupling capacitance was addedUnder major busses and around major gridded clock driversOccupies 15-20% of die area1-F 2-cm2 Wirebond Attached Chip

31、Capacitor (WACC) significantly increases “Near-Chip” de-coupling160 Vdd/Vss bondwire pairs on the WACC minimize inductanceSource: B. Herrick (Compaq)EV6 WACCSource: B. Herrick (Compaq)The Transmission LineThe Wave EquationVinVoutrgcrrxgcrgcgcllllDesign Rules of ThumbTransmission line effects should be considered when the rise or fall time of the input signal (tr, tf) is smaller than the time-of-flight of the transmission line (tflight).tr (tf) 2.5 tflightTransmission line effects should only be considered when the