用加法器代替乘法器并实现流水练习

1、 明德扬科技教育有限公司用加法器代替乘法器并实现流水练习官 网：淘 宝：QQ 群：97925396QQ咨询：158063679目录 TOC o 1-3 h z u HYPERLINK l _Toc452060860 flow_4 PAGEREF _Toc452060860 h 3 HYPERLINK l _Toc452060861 flow_4a PAGEREF _Toc452060861 h 5 HYPERLINK l _Toc452060862 flow_4s PAGEREF _Toc452060862 h 10明德扬科技公司主要是以FPGA为核心，专业从事FPGA配套视频开发板教程、FP

2、GA培训班或其他培训、研发FPGA技术开发、承接FPGA项目开发。欢迎咨询加入明德扬FPGA和ASIC交流群97925396。 明德扬以PDF格式提供源代码，是为了鼓励大家多思考，不要拿来就用，否则是学不好FPGA的。 本代码对应的设计思路，请参考明德扬视频课程。flow_4module flow_4( clk , rst_n , vld_in , a , b , c , d , vld_out, sum ); /参数定义 parameter DAT_W = 4 ; parameter SUM0_W = 8 ; parameter SUM1_W = 8 ; parameter SUM_W =

3、16; /输入信号定义 input clk ; input rst_n ; input vld_in ; input DAT_W-1:0 a ; input DAT_W-1:0 b ; input DAT_W-1:0 c ; input DAT_W-1:0 d ; /输出信号定义 output vld_out; output SUM_W-1:0 sum ; /输出信号reg定义 wire SUM_W-1:0 sum ;wire vld_out; /中间信号定义 wire SUM0_W-1:0 sum0 ; wire SUM1_W-1:0 sum1 ;wire vld_out_0; flow_4

4、s mul_0( .clk (clk ), .rst_n (rst_n ), .a (a ), .b (b ), .vld_in (vld_in ), .vld_out (vld_out_0), .sum (sum0 ) ); flow_4s mul_1( .clk (clk ), .rst_n (rst_n ), .a (c ), .b (d ), .vld_in (vld_in ), .sum (sum1 ) ); /这个8*8乘法器模块flow_4a应该可以和4*4乘法器模块重用，但是没有 /想到怎样用,希望学到后面可以有其他方法 flow_4a mul( .clk (clk ), .r

5、st_n (rst_n ), .a (sum0 ), .b (sum1 ), .vld_in (vld_out_0 ), .vld_out (vld_out), .sum (sum ) );endmoduleflow_4amodule flow_4a( clk , rst_n , a , b , vld_in , vld_out, sum ); /参数定义 parameter DAT_W = 8 ; parameter SUM_W = 16; /输入信号定义 input clk ; input rst_n ; input vld_in ; input DAT_W-1:0 a ; input D

6、AT_W-1:0 b ; /输出信号定义 outputSUM_W-1:0 sum ; output vld_out ; /输出信号reg定义 reg SUM_W-1:0 sum ;reg vld_out ; /中间信号定义 reg vld_out_0; reg vld_out_1; reg vld_out_2; reg vld_out_3; reg vld_out_4; reg vld_out_5; reg vld_out_6; reg vld_out_7; reg DAT_W-1:0 a0 ; reg DAT_W-1:0 a1 ; reg DAT_W-1:0 a2 ; reg DAT_W-1

7、:0 a3 ; reg DAT_W-1:0 a4 ; reg DAT_W-1:0 a5 ; reg DAT_W-1:0 a6 ; reg DAT_W-1:0 b0 ; reg DAT_W-1:0 b1 ; reg DAT_W-1:0 b2 ; reg DAT_W-1:0 b3 ; reg DAT_W-1:0 b4 ; reg DAT_W-1:0 b5 ; reg DAT_W-1:0 b6 ; reg SUM_W-1:0 sum0 ; reg SUM_W-1:0 sum1 ; reg SUM_W-1:0 sum2 ; reg SUM_W-1:0 sum3 ; reg SUM_W-1:0 sum4

8、 ; reg SUM_W-1:0 sum5 ; reg SUM_W-1:0 sum6 ; /vld_out always (posedge clk or negedge rst_n)begin if(rst_n=1b0)begin vld_out_0 = 0; vld_out_1 = 0; vld_out_2 = 0; vld_out_3 = 0; vld_out_4 = 0; vld_out_5 = 0; vld_out_6 = 0; vld_out_7 = 0; vld_out = 0; end else begin vld_out_0 = vld_in; vld_out_1 = vld_

9、out_0; vld_out_2 = vld_out_1; vld_out_3 = vld_out_2; vld_out_4 = vld_out_3; vld_out_5 = vld_out_4; vld_out_6 = vld_out_5; vld_out_7 = vld_out_6; vld_out = vld_out_7; end end /缓存数据a always(posedge clk or negedge rst_n)begin if(rst_n=1b0)begin a0 = 0; a1 = 0; a2 = 0; a3 = 0; a4 = 0; a5 = 0; a6 = 0; en

10、d else begin a0 = a ; a1 = a0; a2 = a1; a3 = a2; a4 = a3; a5 = a4; a6 = a5; end end /缓存数据b always (posedge clk or negedge rst_n)begin if(rst_n=1b0)begin b0 = 0; b1 = 0; b2 = 0; b3 = 0; b4 = 0; b5 = 0; b6 = 0; end else begin b0 = b DAT_W-1:1; b1 = b0DAT_W-2:1; b2 = b1DAT_W-3:1; b3 = b2DAT_W-4:1; b4 =

11、 b3DAT_W-5:1; b5 = b4DAT_W-6:1; b6 = b5DAT_W-7:1; end end /流水线求和运算，代替乘法运算 /第一级将a 赋给 sum0 always (posedge clk or negedge rst_n)begin if(rst_n=1b0)begin sum0 = 0; end else if(b0)begin sum0 = a; end else begin sum0 = 0; end end /第二级 always (posedge clk or negedge rst_n)begin if(rst_n=1b0)begin sum1 = 0

12、; end else begin sum1 = sum0 + (b00?(a0,1b0):0); end end /第三级 always (posedge clk or negedge rst_n)begin if(rst_n=1b0)begin sum2 = 0; end else begin sum2 = sum1 + (b10?(a1,2b0):0); end end /第四级 always (posedge clk or negedge rst_n)begin if(rst_n=1b0)begin sum3 = 0; end else begin sum3 = sum2 + (b20?

13、(a2,3b0):0); end end /第五级 always (posedge clk or negedge rst_n)begin if(rst_n=1b0)begin sum4 = 0; end else begin sum4 = sum3 + (b30?(a3,4b0):0); end end /第六级 always (posedge clk or negedge rst_n)begin if(rst_n=1b0)begin sum5 = 0; end else begin sum5 = sum4 + (b40?(a4,5b0):0); end end /第七级 always (po

14、sedge clk or negedge rst_n)begin if(rst_n=1b0)begin sum6 = 0; end else begin sum6 = sum5 + (b50?(a5,6b0):0); end end /第八级 always (posedge clk or negedge rst_n)begin if(rst_n=1b0)begin sum = 0; end else begin sum = sum6 + (b60?(a6,7b0):0); end end endmoduleflow_4smodule flow_4s( clk , rst_n , a , b ,

15、 vld_in , vld_out, sum ); /参数定义 parameter DAT_W = 4; parameter SUM_W = 8; /输入信号定义 input clk ; input rst_n ; input vld_in ; input DAT_W-1:0 a ; input DAT_W-1:0 b ; /输出信号定义 outputSUM_W-1:0 sum ; output vld_out ; /输出信号reg定义 reg SUM_W-1:0 sum ; reg vld_out ; /中间信号定义 reg vld_out_0; reg vld_out_1; reg DAT

16、_W-1:0 a0 ; reg DAT_W-1:0 a1 ; reg DAT_W-1:0 a2 ; reg DAT_W-1:0 b0 ; reg DAT_W-1:0 b1 ; reg DAT_W-1:0 b2 ; reg SUM_W-1:0 sum0 ; reg SUM_W-1:0 sum1 ; reg SUM_W-1:0 sum2 ; /vld_out always (posedge clk or negedge rst_n)begin if(rst_n=1b0)begin vld_out_0 = 0; vld_out_1 = 0; vld_out = 0; end else begin v

17、ld_out_0 = vld_in ; vld_out_1 = vld_out_0; vld_out = vld_out_1; end end /缓存数据a always(posedge clk or negedge rst_n)begin if(rst_n=1b0)begin a0 = 0; a1 = 0; a2 = 0; end else begin a0 = a ; a1 = a0; a2 = a1; end end /缓存数据b always (posedge clk or negedge rst_n)begin if(rst_n=1b0)begin b0 = 0; b1 = 0; b

18、2 = 0; end else begin b0 = b 3:1; b1 = b02:1; b2 = b11 ; end end /流水线求和运算，代替乘法运算 /第一级将a 赋给 sum0 always (posedge clk or negedge rst_n)begin if(rst_n=1b0)begin sum0 = 0; end else if(b0)begin sum0 = a; end else begin sum0 = 0; end end /第二级 always (posedge clk or negedge rst_n)begin if(rst_n=1b0)begin sum1 = 0; end else begin sum1 = sum0 + (b00?(a0,1