Quartus II 时序约束方法

1、Quartus II Software Design Series: Timing Analysis2常见术语的中文翻译Tsetup: 建立时间Thold：保持时间Skew：传输时差,时钟歪斜Slack：余量Fmax：最大频率Input maximum delay：输入最大延时Input minimum delay：输入最小延时Output maximum delay：输出最大延时Output minimum delay：输出最小延时Max delay ：最大延时Min Delay：最小延时Recovery time：恢复时间Removal time：移去时间Jitter：抖动3TimeQue

2、st AgendaIntroduction to TimeQuestTimeQuest terminology reviewUsing TimeQuestExample Application4TimeQuest Timing AnalyzerNew timing engine in Quartus IIProvide timing analysis solution meeting requirements of all usersFPGA design backgroundASIC design backgroundEasy-to-use interfaceStandard reporti

3、ng & constraint terminology Scripting emphasis5TimeQuest Timing Analyzer (cont.)More accurate analysisrise/fall delaysSDC SupportMore advanced & standardized constraint methodologyEasily supports more complex designs and analysisComplex clocking schemesSource-synchronous designsValidating Performanc

4、e with the TimeQuest Static Timing AnalyzerTimeQuest Terminology Review7TimeQuest Terminology ReviewLaunch & latch edgesArrival time vs. required timeSetup & hold analysisSlackSDC terminology8Path & Analysis TypesThree types of Paths:Clock PathsData PathAsynchronous Paths*Clock PathsAsync PathData P

5、athAsync PathDQCLRPREDQCLRPRETwo types of Analysis:Synchronous clock & data pathsAsynchronous* clock & async paths*Asynchronous refers to signals feeding the asynchronous control ports of the registers9Setup & HoldSetup:The minimum time data signal must be stableBEFORE clock edgeHold:The minimum tim

6、e data signal must be stableAFTER clock edgeDQCLRPRECLKThValidDATATsuCLKDATATogether, the setup time and hold time form a Data Required Window, the time around a clock edge in which data must be stable.10Launch & Latch EdgesCLKLaunch EdgeLatch EdgeData ValidDATALaunch Edge:the edge which “launches”

7、the data from source registerLatch Edge:the edge which “latches” the data at destination register (with respect to the launch edge, typically 1 cycle)11Launch & Latch EdgesLaunch Edge: Clock edge that activates the source register in a register-to-register pathLatch Edge: Clock edge that activates t

8、he destination registerBACLKACLKBCLKACLKBThe relationship between the edges is derived from the user-defined clock settings12Data Arrival TimeThe time for data to arrive at a registers D inputData Arrival Time = launch edge + Tclk1 + Tco +TdataLaunchEdge13Clock Arrival TimeThe time for clock to arri

9、ve at a registers clock inputClock Arrival Time = latch edge + Tclk2 LatchEdge14Data Required Time - SetupTime signal must arrive at destination register to be properly sampledData Required Time = Clock Arrival Time Tsu LatchEdge15Data Required Time - HoldData Required Time = Clock Arrival Time + Th

10、 LatchEdgeEarliest time signal can arrive at destination register and not interfere with data sampled on previous clock edge16SlackSetup Slack = Setup Required Time Data Arrival TimeHold Slack = Data Arrival Time Hold Required TimeSlack must be positive to ensure proper operationEquations work for i

11、nternal and I/O paths17Why is this important?Quartus reports timing using this terminologyNo need to memorize!18Input Maximum DelayMaximum Delay from External Device to Altera I/ORepresents External Device tco + PCB Delay - PCB Clock SkewConstrains Registered Input Path (tsu)AtcotsuAltera DeviceExte

12、rnal DevicePCB DelaytsuA tCLK Input Maximum DelayInput Maximum DelaytsuACLKCLK19Input Minimum DelayMinimum Delay from External Device to Altera I/ORepresents External Device tco + PCB Delay - PCB Clock SkewConstrains Registered Input Path (th)AtcothAltera DeviceExternal DevicePCB DelaythA Input Mini

13、mum DelayInput Minimum DelaythACLKCLK20Output Maximum DelayMaximum Delay from Altera I/O to External DeviceRepresents External Device tsu + PCB Delay - PCB Clock SkewConstrains Registered Output Path (Max. tco)BtcotsuAltera DeviceExternal DevicePCB DelaytcoB tCLK - Output Maximum DelaytcoOutput Maxi

14、mum DelayCLKCLK21Output Minimum DelayMinimum Delay from Altera I/O to External DeviceRepresents External Device th - PCB Board DelayConstrains Registered Output Path (Min. tco)BtcothAltera DeviceExternal DeviceBoard DelaytcoB Output Minimum DelaytcoOutput Minimum DelayCLKCLK22SDC Terminology ReviewT

15、ermDefinitionNodeBasic timing netlist unit (ports, pins, registers or keepers)KeeperPorts or registersCellDevice building blocks (e.g. look-up tables, registers, embedded multipliers, memory blocks, I/O elements, PLLs, etc.)PinInput or outputs of cellsNetConnections between pinsPortTop-level inputs

16、and outputs (e.g. device pins)23SDC Netlist ExampleSample Pin Names:ina|comboutinrega|dataininrega|clkinrega|regoutab|comboutab|datacinainbclkinregainregbabclkclkctrloutregoutcomboutdatainclkdatacdatadinclk0regoutoutclkcomboutdatainSample Net Names:inacomboutabclkclkctrlinregacell=atom/wysiwygpin =

17、otermpin = itermport = I/OnetcellQuartus II Software Design Series: Timing AnalysisTiming Analysis & Settings25How does timing verification work?Every device path in design must be analyzed with respect to timing specifications/requirementsCatch timing-related errors faster and easier than gate-leve

18、l simulation & board testingDesigner must enter timing requirements & exceptionsUsed to guide fitter during placement & routingUsed to compare against actual results INCLKOUTDQCLRPREDQCLRPREcombinational delaysCLR26Timing Analysis AgendaTimeQuest basicsTiming analysis basicsTiming reportsTiming cons

19、traintsExample applications27TimeQuest Timing AnalyzerTiming engine in Quartus II softwareProvides timing analysis solution for all levels of experienceFeaturesSynopsys Design Constraints (SDC) supportStandardized constraint methodologyEasy-to-use interfaceConstraint entryStandard reportingScripting

20、 emphasisPresentation focuses on using GUI28Opening TimeQuestToolbar buttonTools menuStand-alone modequartus_stawCommand line29TimeQuest GUIReport PaneTasks PaneConsole PaneView PaneMenu access to all TimeQuest features30Tasks PaneProvides quick access to common operationsCommand executionReport gen

21、erationExecutes most commands with default settingsUse menus for non-default settingsDouble-click to execute any command31Report PaneDisplays list of generated reports currently available for viewingReports generated by Tasks paneReports generated using report commandsHighlight report to see detail

22、in View window32Timing Summary TableView PaneMain viewing area that displays report table contents & graphical resultsTiming HistogramPath Slack Report33Viewing Multiple ReportsClick & drag + sign to divide view pane into multiple windows34Viewing Multiple Reports ExampleView pane split into two win

23、dowsHighlight window, then highlight report in Reports pane you would like to appear thereDrag bars to edges to remove splitsUse Target Pane button to force a selected report to appear in a pane35Console paneAllows direct entry and execution of SDC & Tcl commandsDisplays equivalent of command execut

24、ed by GUIDisplays TimeQuest output messagesHistory tab records all executed SDC & Tcl commandsCopy & paste to create scripts or SDC files36SDC File Editor = Quartus II Text EditorUse Quartus II editor to create and/or edit SDCSDC editing unique features (for .sdc files)Access to GUI dialog boxes for

25、 constraint entry (Edit Insert Constraint)Syntax coloringTooltip syntax helpTimeQuest File menu New/Open SDC FileQuartus II File menu New Other Files tabPlace cursor over command to see tooltip37SDC File Editor (cont.)Construct an SDC file using TimeQuest graphical constraint creation tools38Basic S

26、teps to Using TimeQuestGenerate timing netlistEnter SDC constraintsCreate and/or read in SDC file (recommended method)orConstrain design directly in consoleUpdate timing netlistGenerate timing reportsSave timing constraints (optional)391) Generate Timing NetlistCreates timing netlist (path database)

27、 based on compilation results Post-synthesis (mapping) or post-fitWorst-case (slow), best-case (fast) timing models, or set operating conditions (needed for Stratix III and Cyclone III devices only)To execute:Netlist menu Tasks paneTcl equivalent of commandTcl: create_timing_netlist402a) Create and/

28、or Read in SDC FileCreate SDC file using SDC file editorRead in constraints & exceptions from existing SDC fileSkip if no SDC fileExecutionRead SDC File (Tasks pane or Constraints menu)File precedence (if no filename specified)Files specifically added to Quartus II project.sdc (if it exists)Tcl: rea

29、d_sdc 412b) Constrain Directly in ConsoleAdd new constraints directlyNot automatically added to SDC fileUse GUI or Console paneNot needed if all constraints in SDC fileRecommend using SDC file (step 2a) instead to ease management and storage of constraintsExample constraints (described in detail lat

30、er)create_clockcreate_generated_clockset_input_delayset_output_delay42Using GUI to Enter Constraints DirectlyMost common constraints can be accessed from the Constraints menuSame as Edit menu Insert Constraints in SDC file editorUse if unfamiliar with SDC syntaxConstraints menu43ConstrainingUser MUS

31、T enter constraints for all paths to fully analyze designTimeQuest only performs slack analysis on constrained design pathsRecommendation: Constrain all paths (clocks & I/O)Not as difficult a task as it may soundWildcardsSingle, generalized constraints cover many paths, even all paths in an entire c

32、lock domain443) Update Timing NetlistApply SDC constraints/exceptions to current timing netlistGenerates warningsUndefined clocksPartially defined I/O delaysCombinatorial loopsUpdate timing netlist after adding any new constraintExecutionUpdate Timing Netlist (Tasks pane or Netlist menu)Tcl: update_

33、timing_netlist454) Generate Timing ReportsVerify timing requirements and locate violationsCheck for fully constrained design or ignored timing constraintsTwo methodsTasks paneAutomatically creates/updates netlist & reads default SDC file if neededReports menuMust have valid netlist to accessTasks pa

34、ne or Reports menuDouble-click on individual report46“Out of Date” ReportsAdding new constraints interactively in console causes current reports to be “out of date”Update timing netlist & regenerate reports (report right-click menu)No such warning when using SDC file47Reset Design CommandLocated in

35、Tasks paneFlushes all timing constraints from current timing netlistFunctional Tcl equivalent: delete_timing_netlist command followed by create_timing_netlistUses“Re-starting” timing analysis on same timing netlist applying different constraints or SDC fileStarting analysis over if results seem to b

36、e unexpected485) Save Timing Constraints (Optional)write_sdc commandSaves all constraints & exceptions applied to current netlist into SDC fileUse if constraints added during TimeQuest session in console instead of SDC fileNotesSDC files generated by TimeQuest only if requestedUse -expand option (no

37、t in GUI) to convert Altera-specific SDC commands into standard SDCRun report_sdc command (console, Tasks pane, or Report menu) to see what will get written to SDC file49Basic Steps to Using TimeQuest (Review)Generate timing netlistEnter SDC constraintsCreate and/or read in SDC file (recommended met

38、hod)orConstrain design directly in consoleUpdate timing netlistGenerate timing reportsSave timing constraints (optional)50Using TimeQuest in Quartus II FlowEnable TimeQuest in Quartus II projectSynthesize Quartus II projectUse TimeQuest to specify timing requirementsVerify timing in TimeQuestPerform

39、 full compilation (run Fitter)51Follow TimeQuest flowUse -post_map argument for synthesis (mapping) only netlistIf design already fully compiled, choose -post_fit (default)Tasks list command defaults to post-fit, so must use Netlist menu in GUIZero IC delays auto-enabled with Post-mapAssumes no inte

40、rconnect delays to determine if it will be possible to meet timingTiming Requirements: Create Post-Map Netlist52Timing Requirements: Enter ConstraintsEnter constraints via Constraints menu or Console paneConstraints menu available in main TimeQuest window and in SDC File Editor53Using TimeQuest in Q

41、uartus II FlowEnable TimeQuest in Quartus II projectSynthesize Quartus II projectUse TimeQuest to specify timing requirementsVerify timing in TimeQuestPerform Full Compilation (run Fitter)54Enabling TimeQuest in Quartus IITells Quartus II to use SDC constraints during fittingFile order precedenceAny

42、 SDC files manually added to Quartus II project (in order).SDC55Enabling TimeQuest in Quartus II SoftwareNotes:Arria GX only supports Timequest.TimeQuest is enabled by default for new Stratix III and Cyclone III designs.56SDC constraints are not stored in QSFTimeQuest can use script to convert QSF t

43、iming assignments to SDC Constraints menuDone automatically if no SDC file exists when first opening TimeQuestSee Quartus II Handbook Chapter, “Switching to the TimeQuest Timing Analyzer” for detailsDifferences between Classic Timing Analyzer and TimeQuestDetails on conversion utilityOnline training

44、 also availableSwitching to the TimeQuest Timing AnalyzerQuartus Settings File (QSF)57Using TimeQuest in Quartus II FlowEnable TimeQuest in Quartus II projectSynthesize Quartus II projectUse TimeQuest to specify timing requirementsVerify timing in TimeQuestPerform full compilation (run Fitter)58Veri

45、fying Timing RequirementsView TimeQuest summary information directly in Quartus II Compilation ReportOpen TimeQuest for more thorough analysisFollow TimeQuest flowRun TimeQuest easy-to-use reporting capabilities (Tasks pane)Many different reporting options available Place Tcl reporting commands into

46、 script fileEasy repetition59TimeQuest Summary ReportsSDC files used during fittingClocks generatedTiming violationsUnconstrained paths603rd-Party Timing Analysis Tool SupportSynopsysPrimeTimeMentor GraphicsTAU61Timing Analysis AgendaTimeQuest basicsTiming analysis basicsTiming reportsTiming constra

47、intsExample applications62Timing Analysis BasicsLaunch vs. latch edgesSetup & hold timesData & clock arrival timeData required timeSetup & hold slack analysisI/O analysisRecovery & removalTiming models63Path & Analysis TypesThree types of Paths:Clock PathsData PathAsynchronous Paths*Clock PathsAsync

48、 PathData PathAsync PathDQCLRPREDQCLRPRETwo types of Analysis:Synchronous clock & data pathsAsynchronous* clock & async paths*Asynchronous refers to signals feeding the asynchronous control ports of the registers64Launch & Latch EdgesCLKLaunch EdgeLatch EdgeData ValidDATALaunch Edge:the edge which “

49、launches” the data from source registerLatch Edge:the edge which “latches” the data at destination register (with respect to the launch edge, typically 1 cycle)65Setup & HoldSetup:The minimum time data signal must be stableBEFORE clock edgeHold:The minimum time data signal must be stableAFTER clock

50、edgeDQCLRPRECLKThValidDATATsuCLKDATATogether, the setup time and hold time form a Data Required Window, the time around a clock edge in which data must be stable.66Setup Slack (contd)Positive slackTiming requirement metNegative slackTiming requirement not met Setup Slack = Data Required Time Data Ar

51、rival Time67Hold Slack (contd)Positive slackTiming requirement metNegative slackTiming requirement not met Hold Slack = Data Arrival Time Data Required Time68FPGA/CPLD or ASSPASSP or FPGA/CPLDI/O AnalysisAnalyzing I/O performance in a synchronous design uses the same slack equationsMust include exte

52、rnal device & PCB timing parametersreg1PRED QCLRreg2PRED QCLRCL*TdataTclk1Tclk2TCOTsu/ThOSCData Arrival PathData Arrival PathData Required Path* Represents delay due to capacitive loading69Recovery & RemovalRecovery:The minimum time an asynchronous signal mustbe stable BEFORE clock edgeRemoval:The m

53、inimum time an asynchronous signal mustbe stable AFTER clock edgeDQCLRSETCLKTremValidASYNCTrecCLKASYNC70Asynchronous = Synchronous?Asynchronous control signal source is assumed synchronousSlack equations still applydata arrival path = asynchronous control pathTsu Trec; Th TremExternal device & board

54、 timing parameters may be needed (Ex. 1)ASSPreg1PRED QCLRFPGA/CPLDreg2PRED QCLROSCFPGA/CPLDreg1PRED QCLRreg2PRED QCLRExample 1Example 2Data arrival pathData arrival pathData required pathData required path71Why Are These Calculations Important?Calculations are important when timing violations occurN

55、eed to be able to understand cause of violationExample causesData path too longRequirement too short (incorrect analysis) Large clock skew signifying a gated clock, etc.TimeQuest uses themEquations to calculate slackTerminology (launch and latch edges, Data Arrival Path, Data Required Path, etc.) in

56、 timing reports72Timing ModelsQuartus II software models device timing at two PVT conditions by defaultSlow Corner ModelIndicates slowest possible performance for any single pathTiming at 85 C junction temp. and VCCMINFast Corner ModelIndicates fastest possible performance for any single pathTiming

57、at 0 C junction temp. and VCCMAXWhy two corner timing models?Ensure setup timing is met in slow modelEnsure hold timing is met in fast modelEssential for source synchronous interfacesThird model (slow, 0 C) available only for Stratix III and Cyclone III devices to support 65 nm and smaller technolog

58、y (temperature inversion phenomenon)73Generating Fast/Slow NetlistSpecify the timing model to be used when creating your netlistDefault is the slow timing netlistTo specify fast timing netlistUse -fast_model option with create_timing_netlist CommandChoose Fast corner in GUI when executing Create Tim

59、ing Netlist from Netlist menuCANNOT run from Tasks Pane74Specifying Operating Conditions Perform timing analysis for different delay models without recreating the existing timing netlistTakes precedence over already generated netlistRequired for selecting slow, 0 C model for Stratix III & Cyclone II

60、IUse get_available_operating_conditions to see available conditions for target device75Timing Analysis AgendaTimeQuest basicsTiming analysis basicsTiming reportsTiming constraintsExample applications76Timing ReportsTiming results available in both the Quartus II Compilation Report and TimeQuestTimeQ