数字设计教学课件第六章组合逻辑设计实践

1、Chapter 6 Combinational Logic Design PracticesMSI building blocks are the important element of combinational circuits.8/22/20221本章重点具备一定功能的通用组合逻辑电路的设计方法及实例掌握常用的MSI的使用方法及功能扩展掌握译码器、MUX实现组合逻辑功能的方法能分析、设计由MSI构建的电路8/22/20222chapter 66.1 Documentation Standard1. Signal Names and Active LevelsMost signals (

2、signal name) have active level. active high active lowNaming convention surffix “_L” attaching to signal name represent active low level. Like, EN_L、READY_L In logic relation, EN_L=EN， READY_L=READY。8/22/20223chapter 62. Active levels for pinsENEN_LDinstartDoutflgstart_LDinDoutflg_LInversion bubbleA

3、ctive lowENENDinstartDoutflgstartDinDoutflgActive hign8/22/20224chapter 6Exp2：EN=1 (active high), data can be transferredEN=0 (active low), data can be transferredENCLKEN_LCLK8/22/20225chapter 63. bubble-to-bubble logic designMake the logic circuit easier to understand.Exp：Not matchABSELDATAABASELDA

4、TAmatch8/22/20226chapter 66.3 Combinational PLDs1. Programmable logic arrays (PLA) two level “ANDOR”device. Can be programmed to realize any sum-of-products logic expression.An nm PLA with p product terms: ninputs moutputs pproduct terms8/22/20227chapter 643 with 6 product termsAND arrayOR array8/22

5、/20228chapter 68/22/20229chapter 62. Programmable Array Logic DevicesFixed OR array，programmable AND arrayBidirectional input/output pins，熔丝型PAL16L8，Output enable8/22/202210chapter 63. Generic Array Logic Devices（GAL）an innovation of the PAL; can be erased and reprogrammed; 8/22/202211chapter 66.4 D

6、ecoderAn important type of combinational circuit .input code wordenable inputOutput code word decodeer1-to-1mapping1-out-of-m codenmn-bitm-bit8/22/202212chapter 61、bianry decodersinput code：n-bitoutput code：2n-bit 2-4 decoder（2-22） I1I0Y3Y2Y1Y0truth table：？Yi：？I1I0Y3Y2Y1Y0000001010010100100111000Yi=

7、miY0=I1I0Y1=I1I0Y2=I1I0Y3=I1I02-4decoderOne input combination chooses an output port.8/22/202213chapter 62-4 decoder with enable inputYi=EN miENI1I0Y3Y2Y1Y0000001000001101001011001001111000I1I0Y3Y2Y1Y0EN2-4 decoder8/22/202214chapter 6（2）74139 , dual 2-4 decoderInput code：B（MSB） A（LSB）Also be called

8、address input.Output code：Y3_LY0_LEN 8/22/202215chapter 6（3）74138, 3-8 decoderEnable inputEN=G1G2A_LG2B_LInput code：C（MSB）、B、 AOutput code： Y0_L Y7_LYi_L=（ENmi）Y0_LY1_LY2_LY3_LY4_LY5_LY6_LY7_LG1G2A_LG2B_LEN8/22/202216chapter 6ENmsblsb8/22/202217chapter 62、realizing combinational circuits with decode

9、rreview：canonical sumDecoder output：Yi_L=(ENmi) when EN=1， Yi_L=mi =Mi add an NAND gate to the decoders output.Exp: (1) F=AB（0、3）F=AB+ABEnable asserted8/22/202218chapter 6（2）if a 3-bit number XYZ is odd number，then ODD output 1，else output 0. realize the function with decoder and gates.solution：F=？F

10、=XYZ（1，3，5，7）8/22/202219chapter 6（3）F=XYZ（0、1、5） 解：8/22/202220chapter 63. Cascading binary decodersHow to construct a 4-16、5-32 decoder？ use multiple 2-4 or 3-8 decoders to cascade.PS.：confirm the number of decoders according to the input and output bits.only one chip works in each decoding.8/22/202

11、221chapter 6Exp：a 4-16 decoderInputs: 4-bit N3、N2、N1、N0。Outputs: 16-bit DEC15_LDEC0_LNeed 2 3-8 decoders. Use the MSB of the inputs as chip-select bit. 000000010111100010011111N3 N2 N1 N0N3 N2 N1 N08/22/202222chapter 6Chip selecting8/22/202223chapter 6Exp：4-bit prime-number detector. Realizing it wi

12、th 74138 and some gates.N3N2N1N0F8/22/202224chapter 64、7-segment decoderClassify of 7-seg displayer：in materials: LED（发光二极管） LCD（液晶）In working mode: common-cathode (共阴极) common-anode (共阳极)afbcegddpabcdedpfggndgnd8/22/202225chapter 67-segment decoder transform the input BCD code to 7-segment displayi

13、ng code.devices： 7446A、74LS47 （驱动共阳） 74LS48、 74LS49（驱动共阴）00001001 are useful input codes.10101111 are unused BCD code.8/22/202226chapter 674LS498/22/202227chapter 65、BCD decoder（二十进制译码器）Inputs: BCDY0Y9BCD decoderOutput:1-out-of 10 code74HC428/22/202228chapter 65.5 Encoder1、binary encoder inputs:1-ou

14、t-of-2n codeI0I1Im(m=2n-1) output:n-bitY0Y1Yn-1binary encoder8/22/202229chapter 68-3 encoderinputoutputI7I6I5I4I3I2I1I0Y2Y1Y01000000011101000000110001000001010001000010000001000011000001000100000001000100000001000In/out:active high8/22/202230chapter 6Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I78/22/20

15、2231chapter 62、Priority Encoderif multiple inputs are asserted, how to deal with?solution：assign priority to each input from high to low. let I7 highest priority and decrease from I6 down to I0 A2,A1,A0encode output IDLEwhen no input is asserted, IDLE=18/22/202232chapter 6inputoutputI7I6I5I4I3I2I1I0

16、A2A1A0IDLE111100111000011010000110000000101100000010100000000100100000000100000000000000018/22/202233chapter 68/22/202234chapter 63、74148 Priority EncoderEI_L：Enable Input.I7_LI0_L：encode input，I7_L has highest priority.A2_LA0_L：encode outputGS_L：GS_L =0 when one or more of the request inputs are as

17、serted.EO_L：enable output, EO_L=0 when all of the request inputs are negative and EI_L=0. 高低优先级8/22/202235chapter 674148真值表8/22/202236chapter 64、cascading priority encoderproblem：how to construct 16-4、32-5 priority encoder？Connecting multiple 8-3 endoder.note： make sure the needed number of chips ac

18、cording to the inputs. need to redesign the output circuit that could produce the correct encoding output.8/22/202237chapter 616-4 priority encoder: use two 74148 U1、U2， U1: input E15_LE8_L; U2: input E7_LE0_L; E15_L is the highest priority, output: A3A0，active high;When one or more inputs is assert

19、ed，GS0=1；and A3A0=0000。U1U28/22/202238chapter 6思考：若需要编码输出、GS0为低电平有效，如何修改电路输出结构？P.413 figure 6-49 shows the 32-5 priority encoders strcture,.8/22/202239chapter 66.6 Three-state Devices1、three-state buffers8/22/202240chapter 6EN_LAOUTENEN_LAAOUT_LOUT_LEnable means: the buffer output normal logic 0、1 w

20、hen EN is asserted；the buffer output Hi-Z when EN is negated. 8/22/202241chapter 6Application data返回时序 address of data source8/22/202242chapter 6Issues in application TPLZ 、TPHZ ：time that takes from normal logic into Hi-Z; TPZL 、TPZH ：time that takes from Hi-Z into normal logic;generally， TPLZ 、TPH

21、Z TPZL 、TPZH But to confirm the correction in application, a control logic is adopted.8/22/202243chapter 674138的相关引脚信号查看电路 截止时间（停滞时间）8/22/202244chapter 6课堂练习试设计一个电路，当控制信号M=1时，电路为“判一致”电路，即当三个输入变量取值全部相同时输入为1；当控制信号M=0时，电路为“多数表决”电路，即输出等于输入变量中占多数的取值。请写出最简表达式。（注：至少要写出卡诺图，三变量为X、Y、Z）8/22/202245chapter 66.7

22、MultiplexerABSELY=A or B2-to-1 MUXY=SELA+SELB8/22/202246chapter 6又称数据选择器，简称MUXOutput:enableselect n data source data output n2s mj：SELj minterm1、基本结构：8/22/202247chapter 6Let b=1, D0D1DjDn-1SELENY8/22/202248chapter 6Exp:4-to-1 MUXABCDS1S001101234outputCS0S1output00A01B10C11D8/22/202249chapter 62、MSI

23、MUX（1）8-to-1 MUX ，74151EN_LaddressY_LY8/22/202250chapter 6返回8/22/202251chapter 6G_L S （2）4-bit, 2 input MUX ，741578/22/202252chapter 6（3）2 bit, 4 input MUX，74 153inputoutput1G_L2G_LBA1Y2Y00001C02C000011C12C100101C22C200111C32C301001C0001011C1001101C2001111C30100002C0100102C1101002C2101102C311001G_L2

24、G_L8/22/202253chapter 63、Expanding MUXsExp1：use 74151 to realize a 16-to-1 MUX, some gates can be used if necessary.Chips needed： according to the 16 inputs, 2 74151 chips.output： combine two chips outputs into one output.8/22/202254chapter 6The MSB(A3) of input act as the chip-select bit.8/22/20225

25、5chapter 6Exp2：用74153实现4输入，4位MUX，。 设4路输入分别是：1D3.0、2D3.0、3D3.0、4D3.0； 4位输出是：Dout3.0 输入选择：S1、S0解：无需外加门，只需要合理安排输入、输出数据端口即可。8/22/202256chapter 6Dout3S1S08/22/202257chapter 64、用MUX实现组合逻辑函数的标准和 multiple input, 1 bit MUX, the output： when EN is asserted： the canonical sum form.74151的内部电路8/22/202258chapter

26、6MUX的数据输入端与真值表的每行输出对应，MUX的地址选择端作为最小项产生器，即 真值表：输出值输入变量 MUX：数据输入端地址端例1：试设计一个数据检测电路，当输入3位二进制数能被3整除时，输出F为1，否则为0。请用74151实现该逻辑函数。 解：F=XYZ（？） 电路？按最小项编号顺序变量与选择端对应8/22/202259chapter 6例1的电路XYZFU1W6D04D13D22D31D415D514D613D712A11C9B10Y5G7VCCGNDR18/22/202260chapter 6例2：若例1中输入数为4位二进制数，如何实现？解1：用16输入，1位的MUX来实现，选用7

27、4150。 F=WXYZ（0，3，6，9，12，15）解2：仍选用74151，先对所求函数的卡诺图做降维处理。预备知识：卡诺图的降维 用一个n变量的卡诺图来处理m变量的函数（nB)F(A=B)F(AB= ABFABFA=BFAB=(A1B1)+(A1=B1) ( A0B0) = A1B1 + (AB+AB)(A1B1 )FA=B=(A1=B1)(A0=B0)FAB=(A1B1)+(A1=B1)(A0BFA=BFABA1B11A1=B1A0B01A1=B1A0=B01伪逻辑8/22/202289chapter 64. 标准MSI比较器4-bit 数值比较器7485级联输入：ALBI、AEBI、AGBI，用于比较器的扩展比较输出（级联输出）：ALBO、AEBO、AGBOAGBO=(AB)+(A=B)AGBIAEBO=(A=B)AEBIALBO=(ABFA=BFABFA=BFABX11.8Y11.8X7.4Y7.4X3.0Y3.08/22/202292chapter 65.10 加法器、减法器和ALU（Adders、Subtractors and ALU）主要内容：二进制补码加/减法的电路实现1、1-bit半加器和全加器（1）半加器XYHSCO0000011010101101半加和：HS=XY进位输出：