课程相关vhdl程序实例

1、VHDL 程序实例2007-1-16目录代数）41、一位加法器（使用2、3-8 译仿真（A5被分配到 Y0-Y7）43、二进制码转变成码54、8-1 多路分配器（二 4-1 和一 2-1 多路分配器5、1-4 多路输出选择器（三 1-2 多路输出选择器） . 6） . 86、1-8 多路输出选择器（一个 1-4 和四个 1-2 多路输出选择器） . 97、1 位全加器（两个半加器和一个或门）118、低电平 2-4 译码（使用代数）12代数）139、2-4 译码（使用10、1，3，5，7 计数器1311、0，2，4，6，8，10，12，14 偶数计数器1412、比较器（使用 WHEN.ELSE）

2、1613、比较器（使用 IF.THEN.ELSE）1614、使用元件15、使用元件16、使用元件 输出选择器元件8-1 多路分配器（二 4-1 和一 2-1 多路分配器1-4 多路输出选择器（三 1-2 多路输出选择器元件）* . 18） . 201-8 多路输出选择器（一个 1-4 多路输出选择器元件和四个 1-2 多路）. 2217、1 位全加器（两个半加器、一个或门元件） . 2518、8 位增计数器2719、2-4 译20、2-4 译21、2-4 译（CASE.IS）28（WITH.SELECT）29（WHEN.ELSE）3022、重复地址译. 3123、1-4 多路输出分配器（CAS

3、E.IS）3124、1-4 多路输出分配器（WITH.SELECT）3225、1-4 多路输出分配器（IF.THEN.ELSE）3326、1-2 多路输出分配器（WHEN.ELSE）3427、1-4 多路输出分配器（WHEN.ELSE）3528、无复位清零 D 触发器3529、同步复位清零 D 触发器3630、带使能端异步复位、置位 D 触发器3731、十六进制减计数器3832、4-2 编33、4-2 编（WITH.SELECT）39（WHEN.ELSE）4034、1-4 多路分配器（IF.ELSE）4135、2 位比较器4236、4-1 多路分配器4237、4-1 多路分配器4438、同或门

4、（IF.THEN.ELSE）4639、1 位全加器（CASE.IS）4740、4 位加法器（FOR）4841、8 位奇偶（奇）发生器4942、4 位右移寄存器（仿真无结果）5043、16 位奇偶（偶位）发生器5144、16 位奇偶（偶位）发生器（编译未通过）*5245、8-1 多路分配器5346、1-4 多路输出分配器5447、8 位异或门（最大 32 位）5548、16 位异或门5649、16 位二进制码转换成码5850、16 位码转换成二进制码5951、5 位 2 进制计数器6152、4 位加法器（出现错误仿真结果）6353、8 位右移寄存器（无复位信号）6554、码到二进制码转换6855

5、、使用达数的半加器6956、JK 触发器6957、监测到“101”输出“1” （未读懂）7158、监测到“0101”输出“1” （未读懂）7259、监测到“0101”或“1001”输出“1” （未读懂）7460、3 位偶数发生器（未读懂）7761、奇偶校验器7962、奇偶校验8063、奇偶校验8264、3-1 多路开关（使用代数）8465、3-1 多路开关（使用真值表）8566、3-1 多路开关（使用 WHEN.ELSE）8667、3-1 多路开关（使用 WITH.SELECT）8668、2 位 2-1 多路开关（使用 CASE.IS）8769、4-1 多路开关（使用 WITH.SELECT）

6、8870、3 输入或非门（使用 WHEN.ELSE）8971、非门8972、程序包（部分程序不能编译）9073、1-8 多路选择器（过程无法通过编译）9574、16 位奇偶校验（过程无法通过编译）9675、D 触发器9776、BCD七段码译. 9877、sh_ro（无法编译）9978、4 位寄存器10079、4 位加法器10180、8 位右移寄存器10281、4 位双向移位寄存器10382、8 位双向移位寄存器10483、BCD 码加计数器10584、4 位双向计数器10685、8 位带使能端双向计数器1078位双向计数器10887、同步清零 D 触发器（不能通过编译）10888、同步清零 D

7、 触发器10989、双输入 2 位寄存器1101、一位加法器（使用代数）-*-* 1 Bit Full Adder UsingAlgebra *-*Filename : ADDER1-*library IEEE;use IEEE.std_logic_1164.all;entity ADDER1 port (X0:Y0:C0:S0:C1:); end ADDER1;isinin inSTD_LOGIC;STD_LOGIC; STD_LOGIC;out STD_LOGIC;out STD_LOGICarchitecture ADDER1_arch of ADDER1 isbeginS0 = X0

8、xor Y0 xor C0;C1 = (X0 and C0) or (X0 and Y0) or (C0 and end ADDER1_arch;Y0);2、3-8 译数据分配器（A5被分配到 Y0-Y7）-*-*-*SN74138 3 TO 8 Decoder SimulationFilename : ALIAS1*-*library IEEE;use IEEE.std_logic_1164.all;entity alias1 isport (A:Y:);end alias1;in STD_LOGIC_VECTOR (5 downto 0);out STD_LOGIC_VECTOR (0 t

9、o7)architecturealias1_arch of alias1 isalia alias aliasbegin:std_logic_vector (2 downto 0)Enable:std_logic_vector (1 downto G:std_logic is A(5);is A (2 downto 0);0) is A (4downto 3);Y(0)Y(1)Y(2)Y(3)Y(4)Y(5)Y(6)Y(7)=G G G G G G GGwhen when when when when when whenwhen(Enable (Enable (Enable (Enable (

10、Enable (Enable (Enable(Enable=0101010101010101and and and and and and andandSel Sel Sel Sel Sel Sel SelSel=000)001)010)011)100)101)110)111)else else else else else else elseelse1;1;1;1;1;1;1;1;end alias1_arch;3、二进制码转变成码-*-*-*Binary To Gray Code Convert *Filename : BOGRA*-*library IEEE;use IEEE.std_l

11、ogic_1164.all;entity BOGRA is port (B: in STD_LOGIC_VECTOR (0 to 7);G: out STD_LOGIC_VECTOR (0 to 7);OGRA;end BarchitectureBOGRA_arch of BOGRA isbeginpros(B)beginfori in G(i)loop;0 to 6 loop= B(i+1) xor B(i);endG(7) = B(7);end pros;end BOGRA_arch;4、8-1 多路分配器（二 4-1 和一 2-1 多路分配器）-*-*-*-*8 To 1 Multipl

12、exer (BLOCK)Two 4 To 1 MUL and One 2 To 1 Filename : BLOCK_1*MUL *-*library IEEE;use IEEE.std_logic_1164.all;entity BLOCK_1 isport (I:S:Y:);end BLOCK_1;in STD_LOGIC_VECTOR (0 to 7);in STD_LOGIC_VECTOR (2 downto out STD_LOGIC0);architectureBLOCK_1_arch of BLOCK_1 issignal X: std_logic_vector (1 downt

13、o 0);beginMUL4_1:BLOCKbeginpros (S,I)beginif S(1 downto 0) X(0) = I(0);elsif S(1 downto X(0) = I(1);elsif S(1 downto X(0) = I(2);elseX(0) =is X(1)X(1)X(1)X(1)=I(4);I(5);I(6);I(7);end case;end pros;end BLOCK MUL4_2;MUL2:BLOCKbeginpros (S,X)beginif S(2) = 0 then Y = X(0);elseY = X(1);end if; pros;ende

14、ndBLOCK MUL2;endBLOCK_1_arch;5、1-4 多路输出选择器（三 1-2 多路输出选择器）-*-*-*-*1 To 4 Demultiplexer (BLOCK)Three 1 To 2 Demultiplexer Filename : BLOCK_2*-*library IEEE;use IEEE.std_logic_1164.all;entity BLOCK_2 port (DIN: S:Y:);end BLOCK_2;isin STD_LOGIC;in STD_LOGIC_VECTOR (1 downto out STD_LOGIC_VECTOR (0 to 3)

15、0);architectureBLOCK_2_arch of BLOCK_2 issignal X:std_logic_vector(1begindownto 0);DEMUL2_1:BLOCKbeginX(0) = DIN when S(1) = X(1) = DIN when S(1) =end BLOCK DEMUL2_1;0 else 1;1 else 1;DEMUL2_2:BLOCKbeginY(0) = X(0) when Y(1) = X(0) whenend BLOCK DEMUL2_2;S(0)S(0)=01elseelse1;1;DEMUL2_3:BLOCKbeginY(2

16、) = X(1) when Y(3) = X(1) whenend BLOCK DEMUL2_3;S(0)S(0)=01elseelse1;1;end BLOCK_2_arch;6、1-8 多路输出选择器（一个 1-4 和四个 1-2 多路输出选择器）-*-*-*-*1One 1ToTo8 Demultiplexer (BLOCK)4 DEMUL And Four 1 To 2 Filename : BLOCK_3*DEMUL *-*library IEEE;use IEEE.std_logic_1164.all;entity BLOCK_3 port (DIN: S:Y:);end BLOC

17、K_3;isin STD_LOGIC;in STD_LOGIC_VECTOR (2 downto 0);out STD_LOGIC_VECTOR (0 to 7)architectureBLOCK_3_arch of BLOCK_3 issignal X:std_logic_vector(0 to 3);beginDEMUL4:BLOCKbeginX(0)X(1)X(2)X(3)=DIN DIN DINDINwhen when whenwhenS(2S(2S(2S(2downto downto downtodownto1)1)1)1)=00011011else else elseelse1;1

18、;1;1;end BLOCK DEMUL4;DEMUL2_1:BLOCKbeginY(0) = X(0) when Y(1) = X(0) whenend BLOCK DEMUL2_1;S(0)S(0)=01elseelse1;1;DEMUL2_2:BLOCKbeginY(2) = X(1) when Y(3) = X(1) whenend BLOCK DEMUL2_2;S(0)S(0)=01elseelse1;1;DEMUL2_3:BLOCKbeginY(4) = X(2) when Y(5) = X(2) whenend BLOCK DEMUL2_3;S(0)S(0)=01elseelse

19、1;1;DEMUL2_4:BLOCKbeginY(6) = X(3) when Y(7) = X(3) whenend BLOCK DEMUL2_4;S(0)S(0)=01elseelse1;1;end BLOCK_3_arch;7、1 位全加器（两个半加器和一个或门）-*-*-*-*1 Bit Full Adder (BLOCK)*Two HAdder And OneFilename : BLOCK_4ate-*library IEEE;use IEEE.std_logic_1164.all;entity BLOCK_4 isport (X0:Y0:C0:C1:S0:);end BLOCK_

20、4;inin inSTD_LOGIC;STD_LOGIC; STD_LOGIC;out STD_LOGIC;out STD_LOGICarchitecture BLOCK_4_arch ofBLOCK_4issignal signal signalbeginCT:ST:CA:std_logic; std_logic;std_logic;HAdder_1:BLOCKbeginCT =ST =end BLOCKX0 and Y0;X0 xor Y0; HAdder_1;HAdder_2:BLOCKbeginCA =ST and C0;S0 = ST xor C0;end BLOCK HAdder_

21、2;OR_GATE:BLOCKbeginC1 = CA or CT; end BLOCK OR_GATE;end BLOCK_4_arch;8、低电平 2-4 译码（使用代数）-*-*-*-*2 To 4 Decoder Active LOW*UsingFilename :Algebra (0)0-*library IEEE;use IEEE.std_logic_1164.all;entityport0is(A:B:Y:);0;ininSTD_LOGIC;STD_LOGIC;out STD_LOGIC_VECTOR (0to3)endarchitecture0_archof0 isbeginY

22、(0)Y(1)Y(2)Y(3)end=not not notnot(not A (not A (A and(A andand and notB);not B);B);B);0_arch;9、2-4 译码（使用代数）-*-*-*-*2 To 4 Decoder Active HIGH*UsingFilename :Algebra (1)1-*library IEEE;use IEEE.std_logic_1164.all;entityport1is(A:B:Y:);1;ininSTD_LOGIC;STD_LOGIC;out STD_LOGIC_VECTOR(0to3)endarchitectur

23、e1_arch of1isbeginY(0)Y(1)Y(2)Y(3)end=notnotAAand and notB;not B; B;B;A andA and1_arch;10、1，3，5，7 计数器-*-*-*Counter 1,3,5,7Filename : C1357*-*library IEEE;use IEEE.std_logic_1164.all;entity C1357 is port (CLK: RESET: Q:);end C1357;in STD_LOGIC; in STD_LOGIC;inout STD_LOGIC_VECTOR(2downto0)architectur

24、e C1357_arch of C1357 isbeginpros (CLK,RESET,Q)beginif RESET = 1 then Q =Q Q Q QQ=011;101;111;001;001;end case;end if;end pros;end C1357_arch;11、0，2，4，6，8，10，12，14 偶数计数器-*-*-*Counter 0,2,4,6,8,10,12,14Filename : CEVEN*-*library IEEE;use IEEE.std_logic_1164.all;entity CEVEN is port (CLK: RESET: Q:);e

25、nd CEVEN;in STD_LOGIC; in STD_LOGIC;out STD_LOGIC_VECTOR (3 downto0)architecture CEVEN_arch of CEVEN issignal REG: std_logic_vector beginpros (CLK,RESET,REG)(3 downto 0);beginif RESET = 1 then REG =REG REG REG REG REG REG REG REGREG=0010;0100;0110;1000;1010;1100;1110;0000;0000;end case; end if;end p

26、ros; Q = REG;end CEVEN_arch;12、比较器（使用 WHEN.ELSE）-*-* Comparator (WHEN . ELSE) *-*Filename : COMPARE1*-*library IEEE;use IEEE.std_logic_1164.all;entity COMPARE1port (isA:B:F:); end COMPARE1;ininSTD_LOGIC;STD_LOGIC;out STD_LOGIC_VECTOR(2 downto0)architecture COMPARE1_arch of COMPARE1 isbeginF B else 0

27、10 when A BLarge elseLargethen= 1;= 0;endend proif;s;pros(A,B)beginif A BSmall elseSmallthen= 1;= 0;endend proif;s;pros(A,B)beginif A =EQVelseEQVB then= 1;=I(0),I(1),I(2),I(3),S(1 downto Y1);0),element2:map (=I(4),I(5),I(6),I(7),S(1 downto Y2);0),element3:map (=Y1,Y2, S(2), Y);end COMPON_1_arch;-*-*

28、-*-*Component Of COMPON_14 To 1 Multiplexer Filename :*-*library IEEE;use IEEE.std_logic_1164.all;entityport (isI: in STD_LOGIC_VECTOR(0 to 3);S: in BIT_VECTOR (1 downto 0);Y: out STD_LOGIC);endarchitecture_arch ofisbeginY = I(0)I(1)I(2)I(3)when when when;S SS=000110else elseelseend_arch;-*-*-*-*Com

29、ponent Of COMPON_1 2 To 1 MultiplexerFilename :*-*library IEEE;use IEEE.std_logic_1164.all;entityportis(I:S:Y:);in STD_LOGIC_VECTORin BIT;out STD_LOGIC(0to 1);endarchitecture_arch ofisbeginY = I(0) when S = 0 else I(1);end_arch;15、使用元件1-4 多路输出选择器（三 1-2 多路输出选择器元件）-*-*-*-*1To 4 Demultiplexer (Componen

30、t) Three 1 To 2 DemultiplexerFilename : COMPON_2*-*library IEEE;use IEEE.std_logic_1164.all;entity COMPON_2 isport (DIN: S:Y:);end COMPON_2;in STD_LOGIC;in STD_LOGIC_VECTOR (1 downto out STD_LOGIC_VECTOR (0 to 3)0);architecture COMPON_2_arch of COMPON_2 iscomponentport(DIN: S:Y:);end component;in ST

31、D_LOGIC; in STD_LOGIC;out STD_LOGIC_VECTOR (0 to 1)signal X: begin element1: element2:element3:STD_LOGIC_VECTOR (0 to 1);portport portmapmap map(DIN,S(1),X);(X(0),S(0),Y(0 to(X(1),S(0),Y(2 to1);3);end COMPON_2_arch;-*-*-*-*Component Of COMPON_2 1 To 2 DemultiplexerFilename :*-*library IEEE;use IEEE.

32、std_logic_1164.all;entityportis(DIN: S:Y:);in STD_LOGIC; in STD_LOGIC;out STD_LOGIC_VECTOR (0 to 1)endarchitecture_arch ofisbeginY(0)Y(1)end=DIN,S(2 downto 1), X);element2:port map (DIN SY=X(0),S(0),Y(0 to 1);element3:port map (DIN SY=X(1),S(0),Y(2 to 3);element4:port map (DIN = X(2),SY= S(0),= Y(4

33、to 5);element5:port map (DINS Y=X(3),S(0),Y(6 to 7);end COMPON_3_arch;-*-*-*-*Component of COMPON_31 To 4 Demultiplexer Filename :*-*library IEEE;use IEEE.std_logic_1164.all;entityportis(DIN: S:Y:);in STD_LOGIC;in STD_LOGIC_VECTOR (1downto0);out STD_LOGIC_VECTOR (0 to3)endarchitecture_arch ofisbegin

34、Y(0)Y(1)Y(2)Y(3)end=DIN DIN DINDINwhen when whenwhenS S SS=00011011else else elseelse1;1;1;1;_arch;-*-*-*-*Component Of COMPON_3 1 To 2 DemultiplexerFilename :*-*library IEEE;use IEEE.std_logic_1164.all;entityport (isDIN: in STD_LOGIC;S:Y:);in STD_LOGIC;out STD_LOGIC_VECTOR (0 to 1)endarchitecture_a

35、rch ofisbeginY(0)Y(1)end=DINDINwhen S = 0 else1;when S = 1 else 1;_arch;17、1 位全加器（两个半加器、一个或门元件）-*-*-*-*1Bit Full Adder (Component) Two Half AdderFilename : COMPON_4*-*library IEEE;use IEEE.std_logic_1164.all;entity COMPON_4 isport (X0:Y0:C0:in ininSTD_LOGIC; STD_LOGIC;STD_LOGIC;S0: out STD_LOGIC; C1

36、: out STD_LOGIC);end COMPON_4;architecture COMPON_4_arch ofCOMPON_4issignal signalsignalCT:ST:CA:STD_LOGIC; STD_LOGIC;STD_LOGIC;componentport(X0:Y0:S0:C1:);in STD_LOGIC; in STD_LOGIC;out STD_LOGIC;out STD_LOGICend component;component OR_GATEport (A:B:F:);in STD_LOGIC; in STD_LOGIC;out STD_LOGICend c

37、omponent;beginport portelement3:OR_GATE portend COMPON_4_arch;mapmap map(X0,Y0,ST,CT);(ST,C0,S0,CA);(CA,CT,C1);-*-*-*-*Component OfCOMPON_4Adder*1 BilfFilename :-*library IEEE;use IEEE.std_logic_1164.all;entityport (isX0: in STD_LOGIC;Y0:S0:C1:);in STD_LOGIC;outoutSTD_LOGIC;STD_LOGICendarchitecture_

38、arch ofisbeginS0 C1end=X0X0 xor Y0;and Y0;_arch;-*-*-*-*Component Of 2 InputFilename :COMPON_4ate OR_GATE*-*library IEEE;use IEEE.std_logic_1164.all;entity OR_GATE isport (A:B:F:);end OR_GATE;in STD_LOGIC; in STD_LOGIC;out STD_LOGICarchitectureOR_GATE_arch ofOR_GATEisbeginF = A or B;end OR_GATE_arch

39、;18、8 位增计数器-*-*8 Bit UP Counter*-*Filename : counter8*-*library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity counter8 port (CLK:Q:isin STD_LOGIC;inout STD_LOGIC_VECTOR (0 in STD_LOGICto7);RESET:);end counter8;architecture counter8_arch of counter8 isbeginpros (CLK,RESET,Q)

40、beginif RESET = 1 then Q = 00000000;elsif CLKevent and CLK = 1 then Q =Y Y Y YY=0111;1011;1101;1110;1111;end case;end pros;end DEC2_4_C_arch;20、2-4 译（WITH.SELECT）-*-* 2 To 4 Decoder (WITH . SELECT) *-*Filename : DEC2_4_S*-*library IEEE;use IEEE.std_logic_1164.all;entity DEC2_4_S is port (A: in STD_L

41、OGIC_VECTOR (1 downto Y: out STD_LOGIC_VECTOR (0 to 3);0);end DEC2_4_S;architecture DEC2_4_S_arch of DEC2_4_Sisbeginwiselect Y = 01111011110111101111when when when whenwhen00,01,10,11,others;end DEC2_4_S_arch;21、2-4 译（WHEN.ELSE）-*-* 2 To 4 Decoder (WHEN . ELSE)*-*Filename :DECOD2_4-*library IEEE;use

42、 IEEE.std_logic_1164.all;entity DECOD2_4 is port (A: in STD_LOGIC_VECTOR (1 downto0);Y: out STD_LOGIC_VECTOR (3 downto 0);end DECOD2_4;architecture DECOD2_4_arch ofDECOD2_4 isbeginY(0)Y(1)Y(2)Y(3)=0=0=0=0when when whenwhenA A AA=00011011else else elseelse1;1;1;1;end DECOD2_4_arch;22、重复地址译-*-* Decode

43、r With Multiple Address*-*Filename : DECORM_S-*library IEEE;use IEEE.std_logic_1164.all;entity DECORM_S is port (S: in STD_LOGIC_VECTOR (2 downto Y: out STD_LOGIC_VECTOR (0 to 4);end DECORM_S;0);architecture DECORM_S_arch of DECORM_S isbeginwithectY =Y Y YY=DIN & 111;1 & DIN & 11;11 & DIN & 1;111 &

44、DIN;end case;end pros;end DEM1_4_C_arch;24、1-4 多路输出分配器（WITH.SELECT）-*-* 1 To 4 Demultiplexer (WITH . SELECT) *-*Filename : DEM1_4_S*-*library IEEE;use IEEE.std_logic_1164.all;entity DEM1_4_S isport (DIN: Y:S:);end DEM1_4_S;in STD_LOGIC;out STD_LOGIC_VECTOR (0 to 3);in STD_LOGIC_VECTOR (1 downto 0)ar

45、chitecture DEM1_4_S_arch of DEM1_4_S isbeginwithectY = DIN & 111 when 1 & DIN & 1111 & DIN & 1111 & DIN when end DEM1_4_S_arch;00,when 01,when 10, others;25、1-4 多路输出分配器（IF.THEN.ELSE）-*-* 1 To 4 Demultiplexer (IF . THEN . ELSE) *-*Filename : DEMUL_IF*-*library IEEE;use IEEE.std_logic_1164.all;entity

46、DEMUL_IF is port (DIN: in STD_LOGIC;S: in STD_LOGIC_VECTOR (1 downto 0);Y: out STD_LOGIC_VECTOR (0 to 3);end DEMUL_IF;architecture DEMUL_IF_arch of DEMUL_IF isbeginpros (DIN ,S)beginif S(1) = 0 thenif S(0)Y =elseY =end if; elseif S(0)Y =elseY =end if; end if;= 0DIN &then111;1 &DIN & 11;= 0then11 & D

47、IN & 1;111 & DIN;end pros;end DEMUL_IF_arch;26、1-2 多路输出分配器（WHEN.ELSE）-*-* 1 To 2 Demultiplexer (WHEN . ELSE) *-*Filename : DEMUL1_2*-*library IEEE;use IEEE.std_logic_1164.all;entity DEMUL1_2 isport (DIN: S:Y:);end DEMUL1_2;in STD_LOGIC; in STD_LOGIC;out STD_LOGIC_VECTOR (0 to 1)architecture DEMUL1_2

48、_arch of DEMUL1_2 isbeginY(0) = DIN when S = 0 else 1; Y(1) = DIN when S = 1 else 1;end DEMUL1_2_arch;27、1-4 多路输出分配器（WHEN.ELSE）-*-* 1 To 4 Demultiplexer (WHEN . ELSE) *-*Filename : DEMUL1_4*-*library IEEE;use IEEE.std_logic_1164.all;entity DEMUL1_4port (isD:S:Y:);end DEMUL1_4;ininSTD_LOGIC;STD_LOGIC

49、_VECTOR (1 downto 0);out STD_LOGIC_VECTOR (0 to 3)architecture DEMUL1_4_arch of DEMUL1_4 isbeginY(0)Y(1)Y(2)Y(3)=D D DDwhen when whenwhenS S SS=00011011else else elseelse0;0;0;0;end DEMUL1_4_arch;28、无复位清零 D 触发器-*-* D Flip Flop With No Reset Clear-*Filename : DFF-*library IEEE;use IEEE.std_logic_1164

50、.all;entity DFF is port (D: CLK: Q:);end DFF;in STD_LOGIC; in STD_LOGIC;out STD_LOGICarchitecture DFF_arch of DFF isbeginpros (CLK)beginif CLKevent and CLK = 1 then Q = D;end if;end pros;end DFF_arch;29、同步复位清零 D 触发器-*-* D F/F With Synchronous CLEAR-*Filename : DFF_CLR-*library IEEE;use IEEE.std_logi

51、c_1164.all;entity DFF_CLR port (D:CLK:isinin inSTD_LOGIC;STD_LOGIC; STD_LOGIC;RESET: Q:);end DFF_CLR;out STD_LOGICarchitecture DFF_CLR_arch of DFF_CLRisbeginpros (CLK,RESET)beginif CLKevent and CLK = 0 then if RESET = 0 thenQ = 0;elseQ = D;end if; end if;end pros;end DFF_CLR_arch;30、带使能端异步复位、置位 D 触发

52、器-*-*-*-*D F/F With Enable andAsynchronous Clear PresetFilename : DLL-*library IEEE;use IEEE.std_logic_1164.all;entity DLLport (D: CLK:isin in in ininSTD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC;STD_LOGIC;RESET: SET: ENABLE:Q:out STD_LOGIC);end DLL;architecture DLL_arch of DLL isbeginpros (CLK,RESET,S

53、ET,ENABLE)beginif RESET = 1 then Q = 0;elsif SET = 1 Q = 1;elsif CLKeventif ENABLEthenand CLK = 1= 1 thenthenQ = D;end if; if;s;endend proend DLL_arch;31、十六进制减计数器-*-*-*HEX DOWN CounterFilename : DOW_COUT*-*library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity DOW_COUT ispor

54、t (CLK: RESET: Q:);end DOW_COUT;in STD_LOGIC; in STD_LOGIC;inout STD_LOGIC_VECTOR (0to3)architecture DOW_COUT_arch of DOW_COUTisbeginpros (CLK,Q,RESET)beginif (RESET = 1) then Q = 0000;elsif CLKevent and CLK = 1 then Q = Q - 1;end if;end pros;end DOW_COUT_arch;32、4-2 编（WITH.SELECT）-*-* 4 To 2 Encode

55、r (WITH . SELECT) *-*Filename : ENC4_2_S*-*library IEEE;use IEEE.std_logic_1164.all;entity ENC4_2_S is port (I: in STD_LOGIC_VECTOR (0 to 3);Y: out STD_LOGIC_VECTOR (1 downto0);end ENC4_2_S;architecture ENC4_2_S_arch of ENC4_2_Sisbeginwith I selectY = 00011011when when whenwhen1000,0100,0010,others;

56、end ENC4_2_S_arch;33、4-2 编（WHEN.ELSE）-*-* 4 To 2 Encoder (WHEN . ELSE) *-*Filename : ENCOD4_2*-*library IEEE;use IEEE.std_logic_1164.all;entity ENCOD4_2 is port (I: in STD_LOGIC_VECTOR (3 downto A: out STD_LOGIC_VECTOR(1 downto);end ENCOD4_2;0);0)architecture ENCOD4_2_arch ofENCOD4_2 isbeginA = 0001

57、1011 ZZ;whenI I II=0001001001001000else else elseelsewhen whenwhenend ENCOD4_2_arch;34、1-4 多路分配器（IF.ELSE）-*-*-*1 To 4 DemultiplexerFilename : DEMUL1_4-*library IEEE;use IEEE.std_logic_1164.all;entity DEMUL1_4 isport (DIN: S:Y:);end DEMUL1_4;in STD_LOGIC;in STD_LOGIC_VECTOR (1 downto0);out STD_LOGIC_

58、VECTOR (0to3)architecture DEMUL1_4_arch of DEMUL1_4isbeginpros (DIN ,S)beginif S(1) = 0 thenif S(0)Y =elseY =end if; elseif S(0)Y =elseY =end if; end if;= 0DIN &then111;1 &DIN & 11;= 0then11 & DIN & 1;111 & DIN;end pros;end DEMUL1_4_arch;35、2 位比较器-*-*-*2 Bit ComparatorFilename : COMPARE*-*library IE

59、EE;use IEEE.std_logic_1164.all;entity COMPARE port (A:B:isin STD_LOGIC;in STD_LOGIC;LARGE: EQV: SMALL:);end COMPARE;outout outSTD_LOGIC;STD_LOGIC; STD_LOGICarchitectureCOMPARE_arch of COMPAREisbeginLARGEEQV SMALL=I (0 to 1),S(0),X(0);element2:MUL2_1port map( (2 to 3),(0),I SF=ISX(1);element3:MUL2_1

60、port map(I = X,S = S(1), F = F);end MUL4_1_arch;-*-* 1 To 2 Multiplexer*-*Filename : MUL2_1-*library IEEE;use IEEE.std_logic_1164.all;entity MUL2_1 isport (I:S:F:);end MUL2_1;in STD_LOGIC_VECTOR in STD_LOGIC;out STD_LOGIC(0 to1);architectureMUL2_1_arch of MUL2_1isbeginF = (not S) and I(0)end MUL2_1_