数字系统设计课件lect1309时序电路

1、1Spring 2013 ZDMC Lec. #1 1Digital System Design I数字系统设计 1Weidong Wang (王维东) Dept. of Information Science & Electronic EngineeringISEEZhejiang University-时序电路2Spring 2013 ZDMC Lec. #1 1任课教师王维东 浙江大学信息与电子工程学系, 信电楼306Zhejiang UniversityDepartment of Information Science and Electronic EngineeringHangzho

2、u, 310027Tel: 86-571-87953170 (O)TA:聂涛： ; Office Hours;Xindian (High-Tech) Building 308.课程简介课程代码：111C0120参考书阎石, 数字电子技术基础, 第5版, 高等教育出版社, 2006.王金明著，数字系统设计与Verilog HDL，电子工业出版社，第4版补充讲义Stanford 大学 108A课程notes.R.H.Katz, G.Borriello, Contemporary Logic Design, second edition,电子工业出版社, 2005.M.M.Mano, 数字设计(第四

3、版), 电子工业出版社, 2010.8/数字系统设计1/2013 教学工作/考核平时30% (课程作业和project，上课出勤率，期中考试)期末闭卷考试 70%答疑信电楼308房间/周二下午2:30-4:30上课课间、课后Email，短信3Spring 2013 ZDMC Lec. #1 34第六章 时序逻辑电路Spring 2013 ZDMC Lec. #1 15Spring 2013 ZDMC Lec. #1 1Sequential Logic时序逻辑介绍（序）Sequential Circuits时序Simple circuits with feedbackLatchesEdge-tr

4、iggered flip-flops啪嗒作响 Timing Methodologies定时Cascading级联 flip-flops for proper operationClock skew时钟偏移 6Spring 2013 ZDMC Lec. #1 1C1C2C3comparatorvalueequalmultiplexerresetopen/closednewequalmux controlclockcomb. logicstateSequential CircuitsCircuits with FeedbackOutputs = f(inputs, past inputs, pas

5、t outputs)Basis for building memory into logic circuitsDoor combination lock is an example of a sequential circuitState is memoryState is an output and an input to combinational logicCombination storage elements are also memory7Spring 2013 ZDMC Lec. #1 1X1X2XnswitchingnetworkZ1Z2ZnCircuits with Feed

6、backHow to control feedback?What stops values from cycling around endlessly8Spring 2013 ZDMC Lec. #1 16.1 概述一、时序逻辑电路的特点功能上：任一时刻的输出不仅取决于该时刻的输入，还与电路原来的状态有关。例：串行加法器，两个多位数从低位到高位逐位相加2. 电路结构上包含存储电路和组合电路存储器状态和输入变量共同决定输出9Spring 2013 ZDMC Lec. #1 1二、时序电路的一般结构形式与功能描述方法10Spring 2013 ZDMC Lec. #1 1可以用三个方程组来描述：1

7、1Spring 2013 ZDMC Lec. #1 1三、时序电路的分类1. 同步时序电路与异步时序电路同步：存储电路中所有触发器的时钟使用统一的clk,状态变化发生在同一时刻异步：没有统一的clk,触发器状态的变化有先有后2. Mealy型和Moore型Mealy型： Moore型： 12Spring 2013 ZDMC Lec. #1 1触发器Flip-Flop分类逻辑功能分类RS锁存器JK触发器T触发器D触发器逻辑功能指按触发器的次态和现态及输入信号之间的逻辑关系.特性表特性方程状态转换图13Spring 2013 ZDMC Lec. #1 1RS 锁存器特性方程Qn+1=S+RQnRS

8、 Latch的状态转换图特性表/真值表01S=1,R=0S=0,R=1S=X,R=0S=0,R=X S R Qn Qn+1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0保持复位置位不定14Spring 2013 ZDMC Lec. #1 1JK 触发器特性方程:Qn+1=JQn+KQnJK FF的状态转换图特性表/真值表01J=1,K=XJ=X,K=1J=X,K=0J=0,K=X J K Qn Qn+1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1

9、 1 1 1 0保持复位置位翻转15Spring 2013 ZDMC Lec. #1 1T 触发器特性方程:Qn+1=TQn+TQnT FF的状态转换图特性表/真值表T触发器：T=1, Qn+1=Qn01T=1T=1T=0T=0 T Qn Qn+1 0 0 0 0 1 1 1 0 1 1 1 0 保持翻转JK触发器的两个输入端连在一起作为T端，可以构成T Flip-flop16Spring 2013 ZDMC Lec. #1 1D 触发器特性方程:Qn+1=DD FF的状态转换图特性表/真值表01D=1D=1D=1D=0 D Qn Qn+1 0 0 0 0 1 0 1 0 1 1 1 1 re

10、setset17Spring 2013 ZDMC Lec. #1 1采用D 触发器实现JK触发器DclkQQKJClk18Spring 2013 ZDMC Lec. #1 1时序逻辑电路时序电路通常包含组合电路和存储电路两部分.存储电路的输出状态反馈到组合电路的输入端，与输入信号一起，共同决定组合逻辑电路的输出.任一时刻的输出信号不仅取决于当时的输入信号，还取决于电路原来的状态（与以前的输入有关）.组合逻辑电路存储电路输出方程Yi驱动方程Zi状态方程 Qi输入Xi时序电路的结构框图19Spring 2013 ZDMC Lec. #1 1时序电路分类同步时序电路所有触发器状态的变化都是在同一个时

11、钟信号下同时发生.异步时序电路触发器状态的变化不是同时发生的.20Spring 2013 ZDMC Lec. #1 1FSM:有限状态机采用输入信号和电路状态的逻辑函数去描述时序电路逻辑功能的方法Mealy型输出信号取决于存储电路状态和输入变量Moore型输出只是存储电路现态的函数输出与时钟同步inputsMoore outputsMealy outputsnext statecurrent statecombinationallogiccombinationallogic21Spring 2013 ZDMC Lec. #1 16.2 时序电路的分析方法6.2.1 同步时序电路的分析方法分析：

12、找出给定时序电路的逻辑功能即找出在输入和CLK作用下，电路的次态和输出。一般步骤：从给定电路写出存储电路中每个触发器的驱动方程（输入的逻辑式），得到整个电路的驱动方程。将驱动方程代入触发器的特性方程，得到状态方程。从给定电路写出输出方程。22Spring 2013 ZDMC Lec. #1 1同步时序电路分析方法目的是找出电路状态和输出信号的变换规律，指出其逻辑功能时序电路求激励方程和输出方程由特征方程求状态方程求状态表画状态图画波形图功能描述23Spring 2013 ZDMC Lec. #1 1例：TTL电路24Spring 2013 ZDMC Lec. #1 16.2.2 时序电路的状态

13、转换表、状态转换图、状态机流程图和时序图一、状态转换表000001000101000100110011100010010101011100110000111100010000010010201003011041000510106110170000011111000025Spring 2013 ZDMC Lec. #1 1二、状态转换图26Spring 2013 ZDMC Lec. #1 1三、状态机流程图（State Machine Chart）见书本26727Spring 2013 ZDMC Lec. #1 1四、时序图28Spring 2013 ZDMC Lec. #1 1例：29Spri

14、ng 2013 ZDMC Lec. #1 1（4）列状态转换表：（5）状态转换图00011011001/010/011/000/1111/100/001/010/030Spring 2013 ZDMC Lec. #1 1*6.2.3 异步时序逻辑电路的分析方法各触发器的时钟不同时发生例：TTL电路31Spring 2013 ZDMC Lec. #1 1同步时序电路分析方法目的是找出电路状态和输出信号的变换规律，指出其逻辑功能时序电路求激励方程和输出方程由特征方程求状态方程求状态表画状态图画波形图功能描述32Spring 2013 ZDMC Lec. #1 1同步时序电路分析例DclkQQDcl

15、kQQxAABBy状态方程: An+1=Ax+Bx Bn+1=Ax状态方程是确定触发器状态转移条件的表达式33Spring 2013 ZDMC Lec. #1 1输出方程 y=(A+B)xDclkQQDclkQQxAABBy34Spring 2013 ZDMC Lec. #1 1状态表描述/状态图 现态 输入 次态 输出 A B x An+1 Bn+1 Y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 现态 次态 输出 x=0 x=1 x=0 x=1

16、 AB AB AB Y 00 00 01 0 0 01 00 11 1 0 10 00 10 1 0 11 00 10 1 000100111ABx/y0/00/11/01/00/11/00/11/0状态图35Spring 2013 ZDMC Lec. #1 1由JK触发器构成的时序电路分析对D触发器,状态方程与输入方程一致.JK/T触发器,参考对应的特性表或特性方程来得到次态值.把触发器输入方程表示成现态和输入变量的函数.列出每个输入方程的二进制数值.利用对应触发器的特性表确定状态表中的次态值.36Spring 2013 ZDMC Lec. #1 1JK FF构成的时序电路分析JKJKCLK

17、xAB JK FF输入方程 JA=B KA=Bx JB=x KB=Ax+Ax37Spring 2013 ZDMC Lec. #1 1JK FF构成的时序电路分析(续)把触发器的输入方程表示成现态和输入变量的函数.将输入方程代入到触发器的特性方程中,得到状态方程.使用对应的状态方程确定状态表中的次态. 现态 输入 次态 触发器输入 A B x A B JA KA JB KB 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 1 1

18、0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 JK FF特性方程: Qn+1=JQn+KQn JK FF输入方程: JA=B KA=Bx JB=x KB=Ax+Ax 状态方程: An+1=AB+AB+AX Bn+1=Bx+ABx+ABx38Spring 2013 ZDMC Lec. #1 1JK FF构成的时序电路分析(续)0011011001000111状态图 现态 输入 次态 触发器输入 A B x A B JA KA JB KB 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 0 1

19、 1 0 0 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 状态方程: An+1=AB+AB+AX Bn+1=Bx+ABx+ABx39Spring 2013 ZDMC Lec. #1 16.3 若干常用的时序逻辑电路6.3.1 寄存器和移位寄存器一、寄存器用于寄存一组二值代码，N位寄存器由N个触发器组成，可存放一组N位二值代码。只要求其中每个触发器可置1，置0。例1：40Spring 2013 ZDMC Lec. #1 1例：用维-阻触发器结构的74HC17541Spring 2013 ZDMC Lec. #

20、1 1二、移位寄存器（代码在寄存器中左/右移动）具有存储 + 移位功能42Spring 2013 ZDMC Lec. #1 143Spring 2013 ZDMC Lec. #1 1器件实例：74LS 194A，左/右移，并行输入，保持，异步置零等功能44Spring 2013 ZDMC Lec. #1 1RDS1S0工作状态0XX置零100保持101右移110左移111并行输入 45Spring 2013 ZDMC Lec. #1 1扩展应用（4位 8位）46Spring 2013 ZDMC Lec. #1 1RSRSRSDQDQDQDQOUT1OUT2OUT3OUT4CLKIN1IN2IN

21、3IN4RS0RegistersCollections of flip-flops with similar controls and logicStored values somehow related (e.g., form binary value)Share clock, reset, and set linesSimilar logic at each stageExamplesShift registersCounters47Spring 2013 ZDMC Lec. #1 1Shift Register: DFF and JK FF48Spring 2013 ZDMC Lec.

22、#1 1clear sets the register contentsand output to 0s1 and s0 determine the shift function s0s1function00hold state01shift right10shift left11load new inputleft_inleft_outright_outclearright_inoutputinputs0s1clockUniversal Shift RegisterHolds 4 valuesSerial or parallel inputsSerial or parallel output

23、sPermits shift left or rightShift in new values from left or right49Spring 2013 ZDMC Lec. #1 1Nth cells0 and s1control mux0123DQCLKCLEARQN-1(left)QN+1(right)InputNto N-1th cellto N+1th cellclears0s1new value10000output001output value of FF to left (shift right)010output value of FF to right (shift l

24、eft)011inputDesign of Universal Shift RegisterConsider one of the four flip-flopsNew value at next clock cycle:50Spring 2013 ZDMC Lec. #1 14位双向移位寄存器74LS194A的逻辑图51Spring 2013 ZDMC Lec. #1 1RSRSRSDQDQDQDQOUT1OUT2OUT3OUT4CLKIN1IN2IN3IN4RS0RegistersCollections of flip-flops with similar controls and log

25、icStored values somehow related (e.g., form binary value)Share clock, reset, and set linesSimilar logic at each stageExamplesShift registersCounters52Spring 2013 ZDMC Lec. #1 1DQDQDQDQINOUT1OUT2OUT3OUT4CLKShift RegisterHolds samples of inputStore last 4 input values in sequence4-bit shift register:5

26、3Spring 2013 ZDMC Lec. #1 1Shift Register Verilogmodule shift_reg (out4, out3, out2, out1, in, clk); output out4, out3, out2, out1; input in, clk; reg out4, out3, out2, out1;always (posedge clk) begin out4 = out3; out3 = out2; out2 = out1; out1 = in; endendmodule54Spring 2013 ZDMC Lec. #1 1Shift Reg

27、ister Verilogmodule shift_reg (out, in, clk); output 4:1 out; input in, clk; reg 4:1 out;always (posedge clk) begin out = out3:1, in; endendmodule55Spring 2013 ZDMC Lec. #1 1Shift Register: DFF and JK FF56Spring 2013 ZDMC Lec. #1 1Register with selective loadWe often use registers to hold values for

28、 multiple clocksWait until neededUsed multiple timesHow do we modify our D flip-flop so that it holds the value till we are done with it?A very simple FSMclkDQenableDQenableclkEn State Next0 Q Q1 Q D57Spring 2013 ZDMC Lec. #1 1IQ: Design Register with Set/ResetSet forces state to 1Reset forces state

29、 to 0What might be a useful fourth option?DQSRS R State Next0 0 Q Q0 1 Q 01 0 Q 11 1 Q X58Spring 2013 ZDMC Lec. #1 1clear sets the register contentsand output to 0s1 and s0 determine the shift function s0s1function00hold state01shift right10shift left11load new inputleft_inleft_outright_outclearrigh

30、t_inoutputinputs0s1clockUniversal Shift RegisterHolds 4 valuesSerial or parallel inputsSerial or parallel outputsPermits shift left or rightShift in new values from left or right59Spring 2013 ZDMC Lec. #1 1Nth cells0 and s1control mux0123DQCLKCLEARQN-1(left)QN+1(right)InputNto N-1th cellto N+1th cel

31、lclears0s1new value10000output001output value of FF to left (shift right)010output value of FF to right (shift left)011inputDesign of Universal Shift RegisterConsider one of the four flip-flopsNew value at next clock cycle:60Spring 2013 ZDMC Lec. #1 1Universal Shift Register Verilogmodule univ_shift

32、 (out, lo, ro, in, li, ri, s, clr, clk); output 3:0 out; output lo, ro; input 3:0 in; input 1:0 s; input li, ri, clr, clk; reg 3:0 out;assign lo = out3;assign ro = out0;always (posedge clk or clr) begin if (clr) out = 0; else case (s) 3: out = in; 2: out = out2:0, ri; 1: out = li, out3:1; 0: out M原理

33、：计数循环过程中设法跳过NM个状态。具体方法：置零法 置数法97Spring 2013 ZDMC Lec. #1 1例：将十进制的74160接成六进制计数器异步置零法工作状态X0XXX置 0（异步）10XX预置数（同步）X1101保持（包括C）X11X0保持（C=0）1111计数98Spring 2013 ZDMC Lec. #1 1例：将十进制的74160接成六进制计数器异步置零法99Spring 2013 ZDMC Lec. #1 1100Spring 2013 ZDMC Lec. #1 1置数法 (a)置入0000 (b)置入1001101Spring 2013 ZDMC Lec. #1

34、 12. N M 的计数器然后再采用置零或置数的方法105Spring 2013 ZDMC Lec. #1 1例：用74160接成二十九进制工作状态X0XXX置 0（异步）10XX预置数（同步）X1101保持（包括C）X11X0保持（C=0）1111计数106Spring 2013 ZDMC Lec. #1 1例：用74160接成二十九进制整体置零（异步）整体置数（同步）107Spring 2013 ZDMC Lec. #1 1四、移位寄存器型计数器1. 环形计数器108Spring 2013 ZDMC Lec. #1 12. 扭环形计数器109Spring 2013 ZDMC Lec. #1

35、 1五、计数器应用实例例1，计数器+译码器顺序节拍脉冲发生器110Spring 2013 ZDMC Lec. #1 1例2，计数器+数据选择器序列脉冲发生器发生的序列：00010111111Spring 2013 ZDMC Lec. #1 1环形计数器电路112Spring 2013 ZDMC Lec. #1 1能自启动的环形计数器电路113Spring 2013 ZDMC Lec. #1 1移位寄存器型计数器的一般结构形式114Spring 2013 ZDMC Lec. #1 1扭环型计数器电路115Spring 2013 ZDMC Lec. #1 1能自启动的扭环形计数器116Spring

36、 2013 ZDMC Lec. #1 1systemdata-pathcontrolstateregisterscombinationallogicmultiplexercomparatorcoderegistersregisterlogicswitchingnetworksSystem Design Hierarchy117Spring 2013 ZDMC Lec. #1 1Two Kinds of FSMsMoore Machine vs Mealy MachineCombinational Logicstatestate(t+1) = F ( state(t), input)Output

37、 (t) = G( state(t), Input )Inputstatestate(t+1) = F ( state(t), input(t)Output (t) = G( state(t)InputState / outInputStateInput / Out118Spring 2013 ZDMC Lec. #1 1Implementation as a sequential digital systemEncoding:how many bits per input value?how many values in sequence?how do we know a new input

38、 value is entered?how do we represent the states of the system?Behavior:clock wire tells us when its ok to look at inputs(i.e., they have settled after change)sequential: sequence of values must be enteredsequential: remember if an error occurredfinite-state specificationresetvalueopen/closednewcloc

39、kstate119Spring 2013 ZDMC Lec. #1 1closedclosedclosedC1=value& newC2=value& newC3=value& newC1!=value& newC2!=value& newC3!=value& newclosedresetnot newnot newnot newS1S2S3OPENERRopenSequential example: abstract controlFinite-state diagramStates: 5 statesrepresent point in execution of machineeach s

40、tate has outputsTransitions: 6 from state to state, 5 self transitions, 1 globalchanges of state occur when clock says its okbased on value of inputsInputs: reset, new, results of comparisonsOutput: open/closed120Spring 2013 ZDMC Lec. #1 1resetopen/closednewC1C2C3comparatorvalueequalmultiplexerequal

41、controllermux controlclockdata-path vs. controlInternal structuredata-pathstorage for combinationcomparatorscontrolfinite-state machine controllercontrol for data-pathstate changes controlled by clockdatapath121Spring 2013 ZDMC Lec. #1 1closedclosedmux=C1resetequal& newnot equal& newnot equal& newno

42、t equal& newnot newnot newnot newS1S2S3OPENERRclosedmux=C2equal& newclosedmux=C3equal& newopenSequential example :finite-state machineFinite-state machinerefine state diagram to include internal structure122Spring 2013 ZDMC Lec. #1 1resetnewequalstatestatemuxopen/closed1S1C1closed00S1S1C1closed010S1

43、ERRclosed011S1S2C2closed00S2S2C2closed010S2ERRclosed011S2S3C3closed00S3S3C3closed010S3ERRclosed011S3OPENopen 0 OPENOPEN open0 ERRERR closednextSequential example: finite-state machineFinite-state machinegenerate state table (much like a truth-table)closedclosedmux=C1resetequal& newnot equal& newnot

44、equal& newnot equal& newnot newnot newnot newS1S2S3OPENERRclosedmux=C2equal& newclosedmux=C3equal& newopenSymbolic statesEncoding?123Spring 2013 ZDMC Lec. #1 1Sequential example: encoding Encode state tablestate can be: S1, S2, S3, OPEN, or ERRneeds at least 3 bits to encode: 000, 001, 010, 011, 100

45、and as many as 5: 00001, 00010, 00100, 01000, 10000choose 4 bits: 0001, 0010, 0100, 1000, 0000Encode outputsoutput mux can be: C1, C2, or C3needs 2 to 3 bits to encodechoose 3 bits: 001, 010, 100output open/closed can be: open or closedneeds 1 or 2 bits to encodechoose 1 bits: 1, 0binaryOne-hothybri

46、d124Spring 2013 ZDMC Lec. #1 1good choice of encoding!mux is identical to last 3 bits of next stateopen/closed isidentical to first bitof stateSequential example :encodingEncode state tablestate can be: S1, S2, S3, OPEN, or ERRchoose 4 bits: 0001, 0010, 0100, 1000, 0000output mux can be: C1, C2, or

47、C3choose 3 bits: 001, 010, 100output open/closed can be: open or closedchoose 1 bits: 1, 0resetnewequalstatestatemuxopen/closed100010010 00000100010010010000100000011000100100100 00001000100100010001000000011001001001000 0001000100100001001000000001101001000 1 0 10001000 10 0000 0000 0next125Spring

48、2013 ZDMC Lec. #1 1resetopen/closednewequalcontrollermux controlclockresetopen/closednewequalmux controlclockcomb. logicstatespecial circuit element, called a register, for remembering inputswhen told to by clockSequential example :controller implementationImplementation of the controller126Spring 2

49、013 ZDMC Lec. #1 1One-hot encoded FSMEven Parity Checker Circuit:In General:FFs must be initialized for correct operation (only one 1)127Spring 2013 ZDMC Lec. #1 1FSM Implementation NotesGeneral FSM form:All examples so far generate output based only on the present state:Commonly called Moore Machin

50、e(If output functions include both present state and input then called a Mealy Machine)128Spring 2013 ZDMC Lec. #1 1Example: Ant BrainSensors: L and R antennae, 1 if in touching wallActuators: F - forward step, TL/TR - turn left/right slightlyGoal: find way out of mazeStrategy: keep the wall on the

51、right129Spring 2013 ZDMC Lec. #1 1Ant Brain130Spring 2013 ZDMC Lec. #1 1A: Following wall, touching Go forward, turning left slightlyB: Following wall, not touching Go forward, turning right slightlyC: Break in wall Go forward, turning right slightlyD: Hit wall again Back to state AE: Wall in front

52、Turn left until.F: .we are here, same as state BG: Turn left until.LOST: Forward until we touch somethingAnt Behavior131Spring 2013 ZDMC Lec. #1 1Designing an Ant BrainState DiagramRC(TR, F)RL RB(TR, F)L RLRA(TL, F)RL RL + RE/G(TL)L + RLOST(F)L R132Spring 2013 ZDMC Lec. #1 1Synthesizing the Ant Brai

53、n CircuitEncode States Using a Set of State VariablesArbitrary choice - may affect cost, speedUse Transition Truth TableDefine next state function for each state variableDefine output function for each outputImplement next state and output functions using combinational logic2-level logic (ROM/PLA/PA

54、L)Multi-level logicNext state and output functions can be optimized together133Spring 2013 ZDMC Lec. #1 1Transition Truth TableUsing symbolic statesand outputsLOST(F)E/G(TL)A(TL, F)B(TR, F)C(TR, F)RRL RRL RLRL RL + RL + RL RstateLRnext stateoutputsLOST00LOSTFLOST1E/GFLOST1 E/GFA00BTL, FA01ATL, FA1 E

55、/GTL, FB 0CTR, FB 1ATR, F.134Spring 2013 ZDMC Lec. #1 1stateLRnext stateoutputsX,Y,ZX, Y, ZFTRTL0 0 0000 0 01000 0 0010 0 1100.0 1 0000 1 11010 1 0010 1 01010 1 0100 0 11010 1 0110 0 11010 1 1001 0 01100 1 1010 1 0110.LOST- 000E/G- 001A- 010B- 011C- 100it now remainsto synthesizethese 6 functionsSyn

56、thesis5 states : at least 3 state variables required (X, Y, Z)State assignment (in this case, arbitrarily chosen)135Spring 2013 ZDMC Lec. #1 1stateinputsnext stateoutputsX,Y,ZL RX+,Y+,Z+FTRTL0 0 0000 0 01000 0 0-10 0 11000 0 01-0 0 11000 0 1000 1 10010 0 1-10 1 00010 0 11-0 1 00010 1 0000 1 11010 1

57、0010 1 01010 1 01-0 0 11010 1 1-01 0 01100 1 1-10 1 01101 0 0-01 0 01101 0 0-10 1 0110e.g. TR = X + Y ZX+ = X R + Y Z R = R TRSynthesis of Next State and Output Functions136Spring 2013 ZDMC Lec. #1 1Circuit ImplementationOutputs are a function of the current state only - Moore machineLRFTRTLNext Sta

58、teCurrent Stateoutputlogicnext statelogicX+Y+Z+XYZ137Spring 2013 ZDMC Lec. #1 1Verilog Sketchmodule ant_brain (F, TR, TL, L, R) inputs L, R; outputs F, TR, TL; reg X, Y, Z; assign F = function(X, Y, Z, L, R); assign TR = function(X, Y, Z, L, R); assign TL = function(X, Y, Z, L, R); always (posedge c

59、lk) begin X = function (X, Y, Z, L, R); Y = function (X, Y, Z, L, R); Z = function (X, Y, Z, L, R); end endmodule138Spring 2013 ZDMC Lec. #1 1Ant is in deep trouble if it gets in this stateDont Cares in FSM SynthesisWhat happens to the unused states (101, 110, 111)?Exploited as dont cares to minimiz

60、e the logicIf states cant happen, then dont care what the functions doif states do happen, we may be in trouble000(F)001(TL)010(TL, F)011(TR, F)100(TR, F)RRL RRL RLRL RL + RL + RL R111101110139Spring 2013 ZDMC Lec. #1 1State MinimizationFewer states may mean fewer state variablesHigh-level synthesis