说明ni官方培训labview rf09rio,fpga and peer-to technology

1、Lesson 9RIO, FPGA, and Peer-to-Peer TechnologyIntroduction to FPGA TechnologyLabVIEW FPGA SystemProgramming Options for LabVIEW FPGANI RF RIO ModulesPeer-to-Peer TechnologyPeer-to-Peer ConfigurationsA. Introduction to FPGA TechnologyWhat is an FPGA?Field programmable gate array (FPGA)A silicon chip

2、with unconnected gatesEnables user to define and re-define functionalityHow does an FPGA work?Defines behavior in softwareCompiles and download to the hardwareExecutes without OSWhen is an FPGA used?Custom hardware or ICs, replacement for ASICs Reconfiguration required after deploymentBenefits of FP

3、GA FlexibilityReconfigurable through softwareTrue parallel processingSimultaneous parallel circuits No CPU time sharing High PerformanceReliabilityOffload processingCostDecision Making in SoftwareTraditional SystemI/OOperating SystemDriver APIApplication SoftwareCalculation25 msResponseOutputsUUTCra

4、sh PossibleDecision Making in HardwareLabVIEW FPGA SystemI/OOperating SystemDriver APIApplication SoftwareCalculation25 ns*ResponseOutputsUUT* Assumes 40 MHz clocksHighest ReliabilityB. LabVIEW FPGA SystemReconfigurable I/O (RIO) HardwareLabVIEW FPGA ModuleNI-RIO Driver LabVIEW FPGA ModuleAdd-on mod

5、ule for LabVIEWDevelop VIs for FPGA targetDevelop VIs for host PC or Real-Time interaction with FPGALabVIEW FPGA: How Does it Work?LabVIEW FPGALabVIEW VIXilinx CompilerVHDLFPGA TargetBitfileUser GeneratedAuto GeneratedBenefits of LabVIEW FPGA SystemFPGA technologyCreate custom hardware using LabVIEW

6、No Verilog/VHDL coding or board designDirect access to hardware terminalsExtensive library of built-in functionsIntegration with third-party IPTools to communicate, monitor and control the FPGA from Windows PC or Real-Time controllerC. Programming Options for LabVIEW FPGALabVIEW FPGANI IPNetLabVIEW

7、FPGA RF Communications LibraryLabVIEW FPGA IP Integration NodeExisting HDL (CLIP Node)IPNet LabVIEW FPGA Functions and Example IP LabVIEW FPGA RF Communications Library1. ModulatorsDemodulatorsChannel Encoders4. Channel Decoders5. Phase Locked Loop6. Fractional Resamplers7. FiltersIP Integration Nod

8、e with Xilinx CoreGenComponent Level IP (CLIP)Allows instantiation of any HDL IP on LabVIEW FPGA targetsNo LabVIEW diagram dataflow restrictionsHDL can run in multiple clock domainsCLIP can interface to the LabVIEW FPGA code Exposes to the user the full capability of the underlying FPGA technologyFP

9、GACLIPCLIPLabVIEW FPGA VICLIP Node FilesIP source code (HDL, netlists, coregen)Constraints file (optional)XML fileUsing the CLIP NodeD. NI RF RIO ModulesNI PXIe-5641R RIO IF Transceiver2 IF Inputs and 2 IF Outputs14-bit ADCs and DACs20 MHz Instantaneous Bandwidth (25 MS/s I/Q)IFs from 3 to 80 MHzXil

10、inx Virtex-5 SX95T LabVIEW-programmable FPGAPXIe-5641R Block DiagramNI PXIe-5641R IF Transceiver ProgrammingTwo methods of programmingLabVIEW FPGA ModuleUser defined, application-specific I/O deviceNI-5640R Instrument DriverNo LabVIEW FPGA programming requiredGeneric Input/Output API configuring mos

11、t module functions NI PXIe-5641R at RF FrequenciesPXI-5600 RF Downconverter9 kHz to 2.7 GHz20 MHz bandwidth at 15 MHz IF-130 to 30 dBm input level80 dB SFDRPXI-5610 RF Upconverter250 kHz to 2.7 GHz20 MHz bandwidth at 25 MHz IF-110 to 10 dB output level PXI-5610PXI-5600PXIe-5641RNI PXIe-5641R Connect

12、ions Digital Trigger Input (SMB)IF Inputs ADC0 and ADC1(SMA)Digital I/O LinesIF Outputs DAC0 and DAC1(SMA)Clock In (SMB) (10 MHz Ref or Ext Sample Clk)NI PXIe-5641R + NI PXI-5600 ConnectionsIF InputExternal 10 MHz Input10 MHz Reference Input to NI PXIe-5641RNI PXI Ref Clk Backplane I/ORF InputIF Out

13、putNI PXIe-5641R + NI PXI-5610 ConnectionsRF Output10 MHz Reference Output to NI PXIe-5641RIF Output from NI PXIe-5641RIF Input from PXIe-5641R10 MHz Reference Input10 MHz Reference Input to NI PXIe-5641RPXIe-5641R for 6.6 GHz Front EndsPXIe-5641R with PXIe-5601 downconverterNot mended because of IF

14、 bandPXIe-5641R with PXIe-5611 IQ modulatorNot mended because no baseband output AC coupledNI PXIe FlexRIO FPGA ModulesVirtex-5 FPGASX95T, SX50T640 DSP48E Slices512 MB onboard DRAM2x 256 MB banks1.6 GB/s per bankPeer-to-peer streaming800 MB/s across PXI Express x4 backplane16 simultaneous streamsUse

15、 as a co-processorE. Peer to Peer (P2P) TechnologyMethod to transfer data directly between hardware devicesStreaming data through Processor not requiredP2P Streaming Architecture3 Basic ComponentsWriterdevice resource that writes data to the streamReaderdevice resource that reads data from the strea

16、mHosts and Host ApplicationsProgrammatically creates streams at run time Manipulates stream connectivity during run time Increases system-level robustness and fault tolerance RF P2P Streaming InstrumentsPXIe-5663(E) VSA10 MHz to 6.6 GHz 16-bit, 150 MS/s 50 MHz bandwidth 250 MB/s streaming to PXI Exp

17、ress FlexRIO PXIe-5673 (E) VSGDual-channel16-bit, 200 MS/s100 MHz bandwidth800 MB/s streaming from PXI Express FlexRIOP2P Single VSG, Single FPGA NI PXIe-5663Signal acquisition sourceNI PXIe-5622 P2P WriterNI PXIe-7965R P2P ReaderProcessing moduleP2P Single VSA, Single VSG NI PXIe-5663Signal acquisi

18、tion sourceNI PXIe-5622 P2P WriterNI PXIe-5673 Signal GenerationNI PXIe-5450 P2P ReaderP2P Single VSA, Single FPGA, Single VSG NI PXIe-5663Signal acquisition sourceNI PXIe-5622 P2P WriterNI PXIe-7965R P2P Reader, WriterProcessing moduleNI PXIe-5673 Signal GenerationNI PXIe-5450 P2P ReaderP2P Dual VS

19、A, Single FPGA Two NI PXIe-5663Signal acquisition sourcesEach NI PXIe-5622 P2P WriterNI PXIe-7965R Two P2P ReadersProcessing modulePXI Express Chassis and P2P StreamingPCIe LinksPCIe SwitchesControllerSingle P2P Stream Same PCIe SwitchIdeal Streaming caseStream depends on the smallest number of link

20、sSource (Digitizer)Sink: FPGA Processing ModuleDual P2P Stream Different PCIe SwitchMax bandwidth depends on controller usedGreater latencySource (Digitizer)Sink: FPGA Processing ModuleDual P2P Stream Same PCIe SwitchPCIe handles case as two separate linksMax bandwidth of 800 MBytes/s for each linkS

21、ource (Digitizer)Source: FPGA Processing ModuleSource: FPGA Processing ModuleSink: FPGA Processing ModuleSink: FPGA Processing ModuleSource (Digitizer)Sink (AWG)Sink (AWG)Embedded Controller Peer-to-Peer RatesControllerMaximum Rate Between LinksNotesNI PXIe-8133 800 MB/sNI PXIe-8130 600 MB/sLimited

22、by chipsetNI PXIe-8106 800 MB/s P2P not supported to/from the rightmost switch on NI PXIe-1075 and NI PXIe-1082 chassis. The NI PXIe-1062Q and NI PXIe-1065 chassis are not affected, since link 4 is used for PCI.NI PXIe-8105Just under 800 MB/sLimitation of PLX 8532 switchNI PXIe-8101 / 02 / 08Not supportedP2P behind switches still worksRaw DataProcessed DataPXIe-5663#1PXIe-7965RHostDMACH0NI 5673 Signal GeneratorWindowFFTScalingWindowFFTScalingPXIe-5663#2RF SignalP2PP2PDMACH1ControlSummaryNational Instruments RIO