嵌入式系统架构软体设计课件

1、嵌入式系统架构软体设计嵌入式系统架构软体设计 -using ARMDay #3,#4,#5 Modules Outline课程介绍Day #3Simple RISC Assembly Language ARM Assembly LanguageARM Development Suite 使用练习Day #4Arm Instruction setImportant ASM Programming SkillsARM/THUMB/C InterworkingDay #5ARM Exception HandlerBuild ARM ROM ImageUse NET-Start! ucLinux BS

2、P嵌入式系统产品设计流程概观ARM system-on-chip Architecture, 2nd ed.ARM architecture reference manual, 2nd ed.ARM Development Suite-Getting StartedARM Development Suite-Developer GuideARM Development Suite-Assembler G/2019嵌入式系统开发经验Building powerful platform with Windows CESoftware Engineering, A pr

3、actitioners Approach 3rd ed.Professional Symbian Programming嵌入式系统架构软体设计 -using ARMModule #3-1: Simple RISC Assembly ConceptRISC精简指令集vs.CISC复杂指令集Hardware instruction decode logicPipeline executionSingle executionLarge microcode ROMs to decode instructionAllow little pipelineMany cycles to completer a

4、 single instructionA smaller die sizeA shorter development timeA higher performance Poor code densityMUO 一个简单的处理器MUO指令集与资料路径指令Opcode功能LDA S0000ACC=memSSTO S0001memS=ACCADD S0010ACC=ACC+memSSUB S0011ACC=ACC-memSJMP S0100PC=SJGE S0101If ACC= PC=SJNE S0110If ACC!=0 PC=SSTP 0111stop指令规则指令执行范例ADD 0 x16AA

5、CC:=ACC+mem0 x16A运算范例C function:Main()C=A+B;MUO 机器指令LDA 0 x100ADD 0 x104STO 0 x108指令Opcode功能LDA S0000ACC=memSSTO S0001memS=ACCADD S0010ACC=ACC+memSSUB S0011ACC=ACC-memSJMP S0100PC=SJGE S0101If ACC= PC=SJNE S0110If ACC!=0 PC=SSTP 0111stop练习： MUO微处理器的运算0 x100 LDA 0 x1000 x002 SUB 0 x1040 x004 STO 0 x1

6、000 x006 JNE 0 x0000 x008 STP请描述此段程式的动作，暂存器值的变化、与资料流。请用C语言来写出这段程式码。指令Opcode功能LDA S0000ACC=memSSTO S0001memS=ACCADD S0010ACC=ACC+memSSUB S0011ACC=ACC-memSJMP S0100PC=SJGE S0101If ACC= PC=SJNE S0110If ACC!=0 PC=SSTP 0111stop嵌入式系统架构软体设计 -using ARMModule #3-2: ARM Assembly LanguageARM7TDMI资料流e.g.r3:=r4+

7、(r4,2)ADD r3,r4,r4,LSL#2 A bus B busARM 的暂存器30 general-purpose, 32 bits registers1 Program Counter (PC)1 Current Program Status Register (CPSR)5 Saved Program Status Registers (SPSR)User mode FIQ mode irq mode SVC mode abort mode undefined modeProgram Status RegisterCPSR: Currrent Program Status Reg

8、iterSPSR: Saved Program Status Register Condition code flags -N: Negative rsult from ALU - Z: Zero result from ALU - C: ALU operation Carried out - V: ALU operation overflowed Inerrupt Disable bits- I: disable the IRQ- F: Disable the FIQ T bit - Architechture xT only- T=0: ARM state - T=1: Thumb sta

9、te Q: Stickly Overflow flag- Architecture 5TE only- QADD, QSUBJ: Processor in Jazelle stateArchitecture 5TEJ onlyMode bitsSpecify the processor mode10000 User10001 FIQ10010 IRQ10011 SVC10111 Abort11011 Undef11111 System31 30 29 28 27 24 7 6 5 4 0N Z C V Q J undefined I F T modeProgram counter R15ARM

10、 state:All ARM instructions are four bytes long (one 32-bit word) and are always aligned on a word boundary.The PC value is stored in bits 31:2 with bits 1:0 undefined.In Thumb state:All instructions are 16 bits wide, and halfword alignedThe PC value is stored in bits31:1 with bits 0 undefined.In Ja

11、zelle state:All instructions are 8 bits wide.The processor performs a word access to read 4 instructions at once.Link Register R14Register 14 is the Link Register (LR).This register holds the address of the next instruction after a Branch and Link (BL) instruction, which is the instruction used to m

12、ake a subroutine call.At all other times, R14 can be used as a general-purpose registerOther Register R0-R13The remaining 15 registers have no special hardware purpose.Their uses are defined purely by software.By convention, ARM assembly language use R13 as Stack Pointer.C and C+ compilers always us

13、e R14 as the Stack Pointer(SP)Structure of ARM Assembly Language ModuleAREA Sectionname,attr,attrStart of New code or data section.CODE: contain machine instructions.READONLY: section should not be written to.Other attr: DATA, NOINIT, READWRITE,Declares an entry point to a program.Labels.Declares th

14、e end of the source file.Calling Subroutines Uses BLBL destination destination is the label on the first instruction of the subroutine.BL does:place the return address in the link register (R14)sets PC to the address of the subroutine.In the subroutinewe can use “MOV pc,lr” to return.By convention,

15、R0-R3 are used to pass parameters.Calling Subroutines Example; name this block of code; mark first instruction; to execute; Set up parameters; Call subroutine; angel_SWI reason_report Exception; ADP_Stopped_ApplicationExit; ARM semihosting SWI; Subroutine code; Return from subroutine.; Mark end of f

16、ileConstant Data TypesNumbers Numeric constants are accepted in three forms:Decimal, for example, 123Hexadecimal, for example, 0 x7Bn_XXX where: n is as base between 2 and 9 xxx is a number in that base.Boolean TRUE and FALSE must be written as TRUE and FALSE.Characters constants consist of opening

17、and closing single quotes X, enclosing either a single character or an escaped character, using the standard C escape characters.Strings consist of opening and closing double quotes “XXXX”. If double quotes or dollar signs are used within a string as literal text characters, they must be represented

18、 by a pair of the appropriate character.For example, you must use $ if you require a single $ in the string. The standard C escape sequences can be used within string constants.Almost all ARM instructions can be conditionally executed.e.g.ADDS r0,r1,r2ADDEQ r0,r1,r2Execute if the N,Z,C and V flags i

19、n the CPSR satisfy a condition specified in the instruction, otherwise, NOP.Conditional ARM InstructionsAlmost every ARM instruction can be executed conditionally on the state of the ALU state flags in the CPSR.Add an S suffix to an ARM data processing instruction to make it update the ALU state fla

20、gs in the CPSRE.g. ADDS r0,r1,r2; r0=r1+r2 and update ALU status in CPSR.In ARM state, you can:update the ALU status flags in the PSR on the result of a data operationexecute several other data operation without updating the flagsexecute following instructions or not, according to the state of the f

21、lags updated in the first operation.In Thumb state most data operations always update the flagsand conditional execution can only be achieved using the conditional branch instruction (B).Do not use the S suffix with CMP, CMN, TST, or TEQ. These comparison instructions always update the flagCondition

22、al ExecutionALU Status Register in CPSRN Set when the result of the operation was Negative.Z Set when the result of the operation was Zero.C when the result of the operation was Carry.A carry occurs if the result of an addition is greater than or equal to 232If the result of a instruction is positiv

23、e,or as the result of an inline barrel shifter operation in a move or logical instruction.V Set when the operation caused oVerflow.Overflow occurs if the result of an add, subtract, or compare is greater than or equal to 231, or less than 231.Q ARM architecture v5Eonly. Sticky flag.Used to detect sa

24、turation in special saturating arithmetic instructions (e.g. QAD, ASUB, QDADD, and QDSUB),Or overflow in certain multiply instructions (SMLAxy and SMLAWy)Conditional Code SuffixesConditional Code ExamplesADD r0,r1,r2;r0=r1+r2, dont update flagsADDS r0,r1,r2;r0=r1+r2, and update flagsADDCSS r0,r1,r2;

25、if C flag set then r0=r1+r2, and update flagsCMP r0,r1;update flags based on r0-r1.Example code sequence:MOV R0,#0LOOP ADD R0, R0, #1CMP R0, #10BNE LOOPSUB R1, R1,R0Write Efficient and small size Code by Conditional InstructionExerciseWrite program by ARM assembly, & evaluate the execution cost in c

26、lock.A Branch needs 3 cycles, others cost 1注：只需使用CMP, SUB, B这三个指令，加上条件式， 就可以完成While (r1!=r2) do if (r1r2)r1=r1-r2; elser2=r2-r1; 嵌入式系统架构软体设计 -using ARM Module #3-3: ARM Development Suite使用练习ARM ADS 1.2Others: C & C+ LibrariesARM firmware suiteAM application libraryRealMonitor: for real time debug mo

27、nitorImplementation IntegrationPre-configured Project Stationary FilesDebugThis build target is configured to built output binaries that are fully debuggable, at the expense of optimization.ReleaseThis build target is debuggable to build output binaries that are fully optimized, at the expense of de

28、bug information.DebugRelThis build target is output binaries that de adequate optimization, and give a good debug view.Possible Development EnvironmentReferenceARM Developer Suie Version 1.2 Getting Started请用Chapter 3练习使用 ADS.嵌入式系统架构软体设计 -using ARM Module #3-4: ARM Instruction SetARM 指令集特点所有指令为32 bi

29、tsADD r0, r1, r2;r0:=r1+r2大部分的指令，可以在一个周期内执行完成指令皆可为有条件式执行Load/store 架构.Thumb 指令集Thumb指令长度为16 bits针对程式码的密度最佳化， 约为65%的ARM code size适合小记忆体系统Thumb指令支援的功能为ARM指令集的一部分执行期间必须切换到Thumb模式ADDSr1,r1,#3ADDr1,#3JazelleJazelle 技术可以让ARM执行8-bit Java Bytecode硬件可以支援到95%的bytecodes速度约为一般软件JVM的五倍ARM 指令集分类Branch instruction

30、sData-processing instructionsLoad and store instructionsStatus register transfer instructionsCoprocessor instructionsException-generating instructions.Branch instructionsB BranchBL Branch with linkStore the return address to r14e.g. CMP r2, #0 BLEQ function function MOV PC, r14Branch Instruction Enc

31、odingThe range of the branch instruction is +/- 32 MbytesL: the branch and link variant.Assembly Format:BLSRmBLSBranch instructions examplee.g. C if (a=0) unction 1 (1);ElsecFunction 1()function2();Function2()return;ASMfunction 1 STMFDr13!, r0-r4, r14 BL function2 LDMFDr13!, r0-r4, pcfunction2 MOV p

32、c, r14Data-processing instructions EncodingAssembly Format:S Rd, Rn,#S Rd, Rn,Rm, shiftData Processing OpodeAssembly Format:SRd, Rn #SRd, Rn Rm, OpcodeMnemonic MeaningEffect24:210000ANDLogical bit-wise AND Rd:=Rn & Op20001 EOR Logical bit-wise excusive ORRd:=Rn EOR Op20010 SUBSubtractRd:=Rn-Op20011R

33、SBReverse subtractRd:=Op2-Rn0100ADDAdd Rd:=Rn+Op20101 ADCAdd with carry Rd:=Rn+Op2+C 0110 SBCSubtract with carry Rd:=Rn-Op2+C-10111RSCReverse subtract with carry Rd:= Op2-Rn+C-11000TSTTest Rd:=Scc on Rn&Op21001TEQTest equivalence Rd:= Scc on Rn EOR Op21010CMPCompare Rd:=Scc on Rn-Op21011CMNCompare n

34、egated Rd:= Scc on Rn+Op21100ORRLogical bit-wise OR Rd:=Rn |Op21101MOVMove Rd:=Op21110BICBit clear Rd:=Rn AND NOT Op21111MVNMove negated Rd:=NOT Op2Example Data-processing InstructionsArithmetic operationsADD r0,r1,r2;r0=r1+r2SUBr0,r1,r2; r0=r1-r2RSBr0,r1,r2; r0=r2-r1Bit-wise logical operationsAND r

35、0,r1,r2; r0 = r1&r2ORRr0,r1,r2; r0 = r1| r2EORr0,r1,r2; r0 = r1 xor r2BICr0,r1,r2; r0 = and not r2; bit clear Example Data-processing Instructions (cont.)Register movement operationsMOV r0,r2; r0=r2MVN r0,r2; r0=not r2Comparison operations (set condition code bits N, Z, C, V)CMP r1,r2; set cc on r1-

36、r2Immediate operandsADD r3,r3,#1 ; r3=r3+1ANDr8,r7, #&ff; r8=r77:0& : base 16ShifterLSL: Logical Left Shift (X2)LSR: Logical Shift Right (/2)ASR Arithmetic Right ShiftROR: Rotate RightShifter Applicationse.g. #1ADD r3,r2,r1, LSL #3;r3:= r2+8*r1e.g. #2r0=r1*5 r0=r1+(r1*4) ADD r0 ,r1, r1, LSL #2Multip

37、ly instruction binary encodingAssembly FormatMULS Rd, Rm, RsMLAS Rd, Rm, Rs, RnS RdHi, RdLo, Rm, RsRdHi: the most significant 32 bits of 64-bit format numberRdLo: the least significant 32 bits of 64-bit format numberOpcode Mnemonic Meaning Effect23:21000 MUL Multiply (32-bit result)Rd:=(Rm*Rs)31:000

38、1 MLA Multiply-accumulate (32-bit result)Rd:=(Rm*Rs+Rn)31:0100 UMULL Unsigned multiply longRdHi:RdLo:=Rm*Rs101 UMLAL Unsigned multiply-accumulate longRdHi:RdLo+=Rm*Rs110 SMULL Signed multiply longRdHi:RdLo:=Rm*Rs111 SMLAL Signed multiply-accumulate longRdHi:RdLo+=Rm*RsAssembly Format:CLZSRd, RmSets

39、Rd to the number of the bit position of hr most significant 1 in Rm. If Rm=0 Rd=32.E.g.MOV r0, #&100CLZr1, R0r1=8Count Leading Zeros Instruction (v5T only)练习用ARM Assembly写一个程式，=mul_包含一个subroutine用来做x10的运算.用ADS环境。不支持具有乘法器功能的ARM Core。main()x=5;y=mul_ten(x);int mul_ten(x)return 10*x; Single Word and Un

40、signed Byte Data Transfer Instruction Binary EncodingAssemble Format:LDR|STRB Rd,Rn, !; Pre-indexed formLDR|STRB Rd,Rn, ; Post-indexed formLDR|STRB Rd,LABEL; PC-relative formLoad and Store ExamplesSingle register and store LDRr0,r1 ;r0:=mem32r1STR r0r1; mem32r1:=r0Base plus offset addressing Pre-ind

41、exing LDR r0,r1, #4 ;r0:=mem32r1+4Auto indexing LDR r0,r1, #4! ;r0:=mem32r1+4, r1=r1+4Post-indexed LDR r0,r1, #4 ;r0:=mem32r1, r1=r1+4PC-relative LDR r1, UART_ADD; UART address into r1 STRBr0,r1; store data to UART UART_ADD &10000000; address literalHalf-word and Signed Byte Data Transfer Instructio

42、n Binary EncodingAssemble Format:LDR|STRH |SH|SB Rd;Rn, ! ; Pre-indexed formLDR|STRH |SH|SB Rd;Rn, ; Post-indexed form An unsigned value is zero-extended to 32 bits when loaded; A singed value is extended to 32 bits by replicating the most significant bit of the data.Half-word Load/Store ExampleADR

43、r1,ARRAY1; half-word array startADR r2,ARRAY2; word array startADR r3,ENDARR1; ARRAY1 end +2LOOP LDRSH r0,r1,#2; get signed half-wordSTR r0,r2,#4; save wordCMP r1,r3; check for end of arrayBLT LOOP; if not finished, loop练习：字串复制写一个Assembly程序做字串复制的动作用ADS环境A=“Hello, this is a sunny day!”B=“ “Multiple R

44、egister Data Transfer Instruction Binary EncodingIn a non-user mode, CPSP may be restored by:LDM|Rn!, Full or empty: The stack pointer can either point to the last item in the stack (a full stack), or the next free space on the stack (an empty stack).Assembly Format:LDM|STM Rn!, IA: Increment after.

45、IB: Increment before.DA: Decrement after.DB: Decrement beforeExample Addressing Mode for LDM/STMISR Examplee.g. Interrupt handler_irq void IRQHandler(void) volatile unsigned int *base=(unsigned int *) 0 x80000000;If (*base=1) C_int_handler_1( ); *(base+1)=( ); IRQHandler PROCSTMFDspl,ro-r4,r12,lrMOV

46、r4,#0 x80000000LDRr0, r4,#0SUBsp,sp,#4CMPr0,#1 BLEQ C_int_handlerMOV r0,#0STR r0,r4,#4ADD sp,sp,#4LDMFD spl,r0-r4,r12,lrSUBSpc,lr,#4Swap Memory And Register Instruction Binary EncodingAssembly Format:SWPBRd,Rm,RnSWP ExampleADR r0,SEMAPHORESWPB r1,r1,r0 ; exchange byter0r1r?0Status Register to Genera

47、l Register Transfer Instruction Binary EncodingAssembly Format:MRSRd,CPSR|SPSRE.g.MRS r0, CPSR; move the CPSR to r0MRS r3, CPSR; move the SPSR to r3Note: The SPSR form should not be used in user or system mode.Transfer to Status Register Instruction Binary EncodingAssembly Format:MRSCPSR_f|SPSR_f, #

48、MRSCPSR_|SPSR_, RmC - the control field PSR7:0X the extension field PSR15:8S the status field PSR23:16F the flags field PSR31:24MSR ExampleSet N,C,V,Z flages:MSRCPSR_f, #&f0000000 ; set all the flagsSet C flag, preserving N,Z, and VMRSr0,CPSR ; move the CPSR to r0ORRr0,r0,#&20000000 ; set bit 29 of

49、r0MSR CPSR_f,r0 : move back to CRSR练习：切换ARM操作模式写一段程序，将ARM由Supervisory mode切换到IRQ mode。用ADS环境。31 30 29 28 27 24 7 6 5 4 0N Z C V Q J underfined I F T mode Mode bits Specify the processor mode 10000User 10001 FIQ 10010 IRQ 10011 SVC 0111Abort 11011 Undef 11111 SystemCoprocessor InstructionsThere are 3

50、 types:Coprocessor data operationsCDP:initiate a coprocessor data processing operationCoprocessor Register transfersMRC:Move to ARM register from coprocessor registerMCR:Move to coprocessor register from ARM registerCoprocessor Memory transferLDC:load coprocessor register from memorySTC:store from c

51、oprocessor register to memoryException-generating & Semaphore InstructionsSWIUsed to cause a Software Interrupt exception to occurSWI SWI 0 x123456BKPTUsed fro software breakpoints in ARM architecture 5 or above. Cause a Prefetch Abort exception to occur.BKPT Summary of ARM ArchitecturesCore Archite

52、ctureARM1v1ARM2v2ARM2as, ARM3v2aARM6, ARM600, ARM610v3ARM7, ARM700, ARM710v3ARM7TDMI, ARM710T, ARM720T, ARM740Tv4TStrongARM, ARM8, ARM810v4ARM9TDMI, ARM920T, ARM940Tv4TARM9ES, XScale Microarchitecturev5TEARM10TDMI, ARM1020Ev5TE926EJ-S/1026EJ-Sv5TEJReferenceS.Furber, ARM system-on-chip Architecture,

53、2nd ed. Addison-WesleySeal. ARM architecture reference manual, 2nd ed. Addison-WesleyARM Development Suite User Guide 嵌入式系统架构与软体设计 using ARMModule #3-5: Important ARM ASM Programming SkillsLoad Constant into RegisterDirect loading with MOV and MVNLoading with LDR Rd,=constDirect Load Constant into R

54、egisterMovcondS,Operand2Load immediate constant to registerE.g.MOV R1,0 x18 ;R1=0 x18Can load any 8-bit constant, giving a range of 0 x00 to 0 xFFMVN: load the bitwise complement of these values. The numerical values are (n+1).Compiler ERROR MSG: Immediate n out of range for this operation.224Loadin

55、g with LDR Rd,=constThe LDR Rd,=const pseudo-instruction can construct any 32-bit numeric constant in a single instructionThe LDR pseudo-instruction generates the most efficient code for a specific constant:If the constant can be constructed with a MOV or MVN instruction, the assembler generates the

56、 appropriate instruction.If the constant cannot be constructed with a MOV or MVN instruction, the assembler:Places the value in a literal pool.Generates an LDR instruction with a program-relative address that reads the constant from the literal pool.e.g.:LDR Rn,pc,#offset to literal pool;load regist

57、er n with one word from the address pc+offsetLiteral Pool: A portion of memory embedded in the code to hold constant values.LDR & Literal Pool Example; ; c:ARMADSv1_2Examplesasmloadcon.sAREALoadcon, CODE, READONLYENTRYSTARTBLfunc1BLfunc2stopMOVr0,#0 x18; =MOV R0, #42LDRr1, =0 x20196SWI0 x123456func1

58、LDRr0, =42; =MOV R0, #42LDRr1, =0 x55555555; =LDR R1, PC, #offset to Literal Pool lLDRr2, =0 xFFFFFFFF; =MVN R2, #0MOVpc, lrLTORGLitetal Pool l constainsLitetal 0 x55555555func2LDRr3, =0 x55555555; =LDR R3, PC, #offset to Literal Pool lLDRr4, =0 x66666666; If this is uncommented it is out of reach;

59、fails, because Literal Pool 2MOV pc, lrLargeTableSPACE4200; Starting at the current location; clears a 4200 bytes area of memory; to zero, reserves a zeroed block of memory; Literal Pool 2 is emptyENDLoading Addresses into RegistersDirect loading with ADR and ADRLLoading addresses with LDR Rd, =labe

60、l.Direct Loading with ADRThe assembler converts an ADR Rn, label pseudo-instruction by generating:A single ADD or SUB instruction that loads the address, if it is in rangeAn error message if the address cannot be reached in a single instruction.The offset range is 255 bytes for an offset to a non wo