数字逻辑设计复习：lesson 3

1、2015.06.15 UESTC数电加油站lesson-3课程内容计数器概念以及应用移位寄存器的概念以及应用Counter(计数器)(P710)The name counter is generally used for any clocked sequential circuit whose state diagram contains a single cycle, as in Figure 8-26. The modulus of a counter is the number of states in the cycle. A counter with m states is call

2、ed a modulo-m counter or, sometimes, a divide-by-m counter. A counter with a nonpower-of-2 modulus has extra states that are not used in normal operation. 计数器的分类按时钟：同步、异步按计数方式：加法、减法、可逆按编码方式：二进制、十进制BCD码、循环码计数器的功能计数、分频、定时、产生脉冲序列、数字运算本节内容行波计数器、同步计数器MSI型计数器及其应用二进制计数器状态的译码8.4.1 Ripple Counterswhen a part

3、icular bit changes from 1 to 0, it generates a carry to the next most significant bit. The counter is called a ripple counter because the carry information ripples from the less significant bits to the more significant bits, one bit at a time. 00-01-10-11-008.4.1 Ripple Counters（行波计数器） use T flip-fl

4、opQ* = QQQT考虑二进制计数顺序：只有当第 i-1 位由10时，第 i 位才翻转。CLKQQTQQTQQTQQTQ0Q1Q2Q3T flip-flop changes state (toggles) on every rising edge of its clock input. 8.4.2 Synchronous Counters(同步计数器)A synchronous counter connects all of its flip-flop clock inputs to the same common CLK signal, so that all of the flip-fl

5、op outputs change at the same time, after only tTQ ns of delay. synchronous counter同步二进制加法计数器1 0 1 1 0 1 1+ 11 0 1 1 1 0 0在多位二进制数的末位加 1，仅当第 i 位以下的各位都为 1 时，第 i 位的状态才会改变。最低位的状态每次加1都要改变。EN QT Q 利用有使能端的 T 触发器实现：Q* = ENQ + ENQ = EN Q通过EN端进行控制，需要翻转时，使 EN = 1 ENi = Qi-1 Qi-2 Q1 Q0EN0 = ? 1synchronous count

6、er1CLKQ0Q1Q2C8.4.3 MSI counters and applications MSI型计数器及应用-同步4位二进制计数器74x163CLR同步清零LD同步预置数RCO进位输出ENPENT使能端进位输出清零8.4.3 MSI Counters and Applications4位二进制计数器74x16374x163的功能表01111CLK工作状态同步清零同步置数保持保持,RCO=0计数CLR_LLD_LENP ENT0111 0 1 0 1 174x161异步清零Other MSI counters1bit BCD counter 74x160 Synchronous cle

7、ar 、74x162 Asynchronous clear 01234567890QAQBQCQD74x160、74x162 the counting sequence is modified to go to state 0 after state 9. In other words, these are modulo-10 counters, sometimes called decade counters.the QD and QC outputs have one-tenth of the CLK frequency, they do not have a 50% duty cycle

8、.Other MSI counters74x169-up/down counterUP/DNUP/DN = 1 counts up （升序）UP/DN = 0 counts down（降序）Enable inputsripple carry outActive-lowABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSRC0SRC1SRC2P0P1P7SDATA如何控制地址端自动轮流选择输出Y0Y7 application of the counterTiming diagram for a modulo-8 binary counter and de

9、coder,showing decoding glitches. 若在一次状态转移中有2位或多位计数位同时变化，译码器输出端可能会产生“尖峰脉冲” 功能性冒险01234567012Modulo-m counterUse SSI device Clocked Synchronous State-Machine DesignUse MSI counter using n bit binary counter as a modulo-m counter in two cases： m 2nAlthough the 163 is a modulo-16 counter, it can be made

10、to count in a modulus less than 16 by using the CLR_L or LD_L input to shorten the normal counting sequence. Cascading 74x163s(计数器的级联)CLOCKRESET_LLOAD_LCNTEND0D1D2D3Q4Q5Q6Q774x16374x16374x16274x162个位十位计数范围： 0-255计数范围：099EXERCISE 1八.74X163 is a synchronous 4-bit binary counter with synchronous load a

11、nd synchronous clear inputs, the basic function table is shown as follow. Design a modulo-10 counter, using one 74X163 and some necessary gates, and the counting sequence is 2-4-2-1BCD. Complete the design and draw a logic diagram. ANSWER:LD_L=(QDQCQBQA)D=QDC=QCB=QBA=QA九、Clocked Synchronous State Ma

12、chine Design（15） 74x163 is a synchronous 4-bit binary counter with synchronous CLEAR input and LOAD input. LD_L=(QBQC), CLR_L=(QDQB ) in the following circuit.1. Finish the logic circuit.2. Draw the state diagram with all states of “Q3Q2Q1Q0” . (“Q3Q2Q1Q0” is the output of 74x163)3. Write the sequen

13、ce of Y. Y is the output of 74x151. (Assumed state of 74x163 start in Q3Q2Q1Q0=0000.) EXERCISE 2V. Design a variable modulus counter only with 74x163, which will be a module-6 counter when the input control signal M = 1 or a module-8 counter when M = 0. The states of module-6 counter should be（11,12

14、,13,14,15,0）.The states of module-8 counter should be (9,10,11,12,13,14,15,0）. (10)Please write out the input equations of LD_L, A, B, C, D. ( 5) Draw the circuit line linked of 74x163.(5) EXERCISE 3【Solution】：the input equations: LD_L=应该检测0000状态 D=A=1 C=0 B=M EXERCISE 4A shift register is an n-bit

15、register with a provision for shifting its stored data byone bit position at each tick of the clock. 8.5 Shift Registersan MSI 4-bit bidirectional, parallel-in, parallel-out shift register (4位双向移位寄存器74x194) CLKCLRS1S0LIND QDC QCB QBA QARIN74x194left-in 左移输入right-in 右移输入left means “in the direction f

16、rom QD to QA,” right means “in the direction from QA to QD.”Function table for the74x194 4-bit universalshift register CLKCLRS1S0LIND QDC QCB QBA QARIN74x194 CLKCLRS1S0LIND QDC QCB QBA QARINCLKCLRS1S0LINRIN移位寄存器的扩展并行输入（8位）并行输出8位8.5.5 Shift-Register Counters(移位寄存器计数器)D0 = F ( Q0 , Q1 , , Qn-1 )Feedba

17、ck logicD Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF3一般结构： 1000010000010010有效状态其他状态8.5.6 Ring Counters (环型计数器)D Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF31000010000010010D0 D1 D2 D3 非自启动的无效状态D0 = Qn-1self-correcting counter self-correcting counter is designed so that all abnormal states have tr

18、ansitions leading to normal states. Self-correcting counters are desirable for the same reason that we use a minimal-risk approach to state assignment : If something unexpected happens, a counter or state machine should go to a “safe” state. 有效状态无效状态D Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF3100

19、0010000010010D0 D1 D2 D3self-correcting自启动的,自校正的Self-correcting 4-bit,4 state ring counter with a single circulating 1Q0Q1Q2Q310CLOCKQ0Q1Q2Q3101000Q0Q1Q2Q3RESET载入Q0Q1Q2Q3CLOCK自校正的RING COUNTER(P735)The major appeal of a ring counter for control applications is that its states appear in 1-out-of-n dec

20、oded form directly on the flip-flop outputs. That is,exactly one flip-flop output is asserted in each state. Furthermore, these outputs are “glitch free”. For the general case, an n-bit self-correcting ring counter uses an n-1-input NOR gate, and corrects an abnormal state within n - 1 clock ticks.S

21、hift-Register Counters一般结构：反 馈 逻 辑D0 = F ( Q0 , Q1 , , Qn-1 )环形计数器：1000010000100001最简单的：D0 = Qn-1反 馈 逻 辑自校正的：D0 = (Qn-2 + + Q1 + Q0)0111101111011110(Qn-2 Q1 Q0) D Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF3Q3Q0Q2Q1Q0 Q1 Q2 Q3Johnson Counter（扭环计数器）D Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF3D0 =

22、 Qn-100001000110011101111011100110001无效有效的状态循环JOHNSON COUNTER：最简单的实现：D0 = Qn-1D Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF31001010010101101011010110101001000001000110011101111011100110001有效状态无效状态如何得到自校正的扭环计数器？Q3Q0Q2Q1Q0 Q1 Q2 Q3Johnson counter(P533)An n-bit shift register with the complement of th

23、e serial output fed back into the serial input is a counter with 2n states and is called a twisted-ring, Moebius, orJohnson counter.An n-bit Johnson counter has 2n - 2n abnormal states, and is therefore subject to the same robustness problems as a ring counter. dddddddd最小成本self-correcting1、确定有效的状态循环

24、2、对无效状态进行处理， 使其进入有效循环。Q0 Q1 Q2 Q31111000011110000Q0Q100 01 11 1000011110Q2Q3D0100001000110011101111011100110001有效无效100101001010110101101011010100101D0 = Q3 + Q2Q0Self-correcting 4-bit,8 state Johnson counter S1S0 wired as a shift-left shift register(接成左移形式)自校正改进：（法一）LIN = Q3 + Q2Q0 CLKCLRS1S0LIND QD

25、C QCB QBA QARIN74x194+5VCLOCKRESET_LQ0Q1Q2Q3Johnson counterself-correcting1、确定有效的状态循环2、对无效状态进行处理， 使其进入有效循环。Q0 Q1 Q2 Q300001000110011101111011100110001有效无效10010100101011010110101101010010可利用置数法。自校正改进： （法二）利用置数每当电路Q3Q2Q1Q0出现0XX0就置数到下一状态0001D0 = Q3.Q0Self-correcting 4-bit,8 state Johnson counter CLKCLR

26、S1S0LIND QDC QCB QBA QARIN74x194+5VCLOCKRESET_L自校正改进：（法二）利用置数每当电路Q3Q2Q1Q0出现0XX0就置数到下一状态0001,S0 = Q3.Q0Q0Q1Q2Q300018.5.6 Linear Feedback Shift Register Counters线性反馈移位寄存器（LFSR）计数器LFSR计数器 有 2n-1 种有效状态 最大长度序列发生器反 馈 逻 辑D Q CK QD Q CK QD Q CK QD Q CK QCLKFF0FF1FF2FF3移位寄存器型计数器的一般结构RESET_LCLOCKLFSR n -bit L

27、inear Feedback Shift Register Counters a maximum-length sequence generator. 奇校验电路全0态的下一状态？反馈方程 P535 表8-21LFSR计数器 有 2n-1 种有效状态 最大长度序列发生器LFSR counter example: 3 bits Shift register counters Q0Q1Q2移位寄存器应用 Shifting the stored data to the next flip-flopApplications: Delay line Data may be reusedSequentia

28、l signal detector序列检测器Data not be reusedSequential signal detector序列检测器顺序脉冲发生器利用移位寄存器构成（无毛刺） 注意自校正（环形计数器 ）利用计数器和译码器构成 注意“毛刺”（二进制计数器的状态译码 ）CLKQ0Q1Q2Q3序列信号发生器 用于产生一组特定的串行数字信号例：设计一个 110100 序列信号发生器利用触发器利用计数器利用移位寄存器利用D触发器设计一个110100序列信号发生器1、画状态转换图2、状态编码000101 表示 S0 S5S0S1S5S2S4S3/1/1/0/1/0/03、列状态转换输出表0 0 00 0 10 1 00 1 11 0 01 0 10 0 10 1 00 1 11 0 01 0 10 0 0Q2Q1Q0Q2*Q1*Q0*Y1101004、得到激励方程和输出方程 考虑未用状态的处理5、得到电路图000001用计数器和数据选择器构成序列信号发生器74x163 CLKCLRLDENPENTA QAB QBC QCD QD RCOENABCD0D1D2D3D4D5D6D7YY