VHDL与数字集成电路设计VHDL2-4

1、2.1 2.1 数字系统的数字系统的基本运算单元基本运算单元2.2 2.2 开关电路与开关电路与CMOSCMOS结构结构2.3 2.3 静态分析：最大集成设计静态分析：最大集成设计2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理第二章第二章 数字集成电路数字集成电路的基本的基本单元单元VHDL与数字集成电路设计与数字集成电路设计MOS器件的动态特性器件的动态特性晶体管每个极都表现出对地电容晶体管每个极都表现出对地电容2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理输入电容由栅极电容构成；输入电容由栅极电容构成；输出电容由漏、源极电容构成。输出电容

2、由漏、源极电容构成。CMOS器件的动态特性器件的动态特性2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理 当状态发生变化，电容需要进行充放电，电流由导通支路当状态发生变化，电容需要进行充放电，电流由导通支路提供，流过导通电阻提供，流过导通电阻2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理 电容充放电过程导致状态电容充放电过程导致状态变化（信号传递）出现延迟；变化（信号传递）出现延迟； 延迟时间与电容大小成正比，延迟时间与电容大小成正比，也与逻辑面积成正比。也与逻辑面积成正比。逻辑单元的延迟时间逻辑单元的延迟时间ACT2.4 2.4 动态分析：延

3、迟时间及缓冲处理动态分析：延迟时间及缓冲处理逻辑单元的延迟时间逻辑单元的延迟时间2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理tpHL = f(Ron.CL)= 0.69 RonCLVoutVoutRnRpVDDVDDVin5VDDVin50(a) Low-to-high(b) High-to-lowCLCL逻辑单元的延迟时间逻辑单元的延迟时间2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理00.511.522.5x 10-10-0.500.511.522.53t (sec)Vout(V)tp = 0.69 CL (Reqn+Reqp)/2?t

4、pLHtpHL2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理CLIf CL is given:- How many stages are needed to minimize the delay?- How to size the inverters?May need some additional constraints.InOut2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理LoadDelayCintCLDelay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)= De

5、lay (Internal) + Delay (Load)CN = CunitCP = 2Cunit2WW2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理/1/10intftCCCkRtCCRDelaypintLWpLintWCint = Cgin with 1f = CL/Cgin - effective fanoutR = Runit/W ; Cint =WCunittp0 = 0.69RunitCunit2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理CLInOut12Ntp = tp1 + tp2 + + tpNjginjginunitu

6、nitpjCCCRt,1,1LNginNijginjginpNjjppCC CCttt1,1,1,01,12.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理Delay equation has N - 1 unknowns, Cgin,2 Cgin,NMinimize the delay, find N - 1 partial derivativesResult: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1Size of each stage is the geometric mean of two neighbors- each stage ha

7、s the same effective fanout (Cout/Cin)- each stage has the same delay1,1,jginjginjginCCC2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理CL= 8 C1InOutC11ff2283fCL/C1 has to be evenly distributed across N = 3 stages:2.4 2.4 动态分析：反相器功耗动态分析：反相器功耗 Dynamic Power Consumption Short Circuit Currents LeakageCharging and

8、Discharging CapacitorsShort Circuit Path between Supply Rails during SwitchingLeaking diodes and transistors2.4 2.4 动态分析：反相器损耗动态分析：反相器损耗Energy/transition = CL * Vdd2Power = Energy/transition * f = CL * Vdd2 * fNeed to reduce CL, Vdd, and f to reduce power.VinVoutCLVddNot a function of transistor siz

9、es!动态损耗动态损耗2.4 2.4 动态分析：反相器损耗动态分析：反相器损耗短路损耗短路损耗VinVinVoutVoutC CL LVddIVDD (mA)0.150.100.05Vin (V)5.04.03.02.01.00.02.4 2.4 动态分析：反相器损耗动态分析：反相器损耗短路损耗短路损耗负载电容越小，短路电流反而越大！2.4 2.4 动态分析：反相器损耗动态分析：反相器损耗反向漏电损耗反向漏电损耗V Vo ou ut tVddSub-ThresholdCurrentDrain JunctionLeakageSub-Threshold Current Dominant Facto

10、rNp+p+Reverse Leakage Current+-VddGATEIDL = JS AJS = 1-5pA/m2 for a 1.2m CMOS technologyJs double with every 9oC increase in temperature 与非门与非门2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理AOutVDDGNDB2-input NAND gateBVDDA逻辑单元的并行设计逻辑单元的并行设计2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理DCBADCBACLC3C2C1 Distributed RC mo

11、del (Elmore delay)tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)Propagation delay deteriorates rapidly as a function of fan-in quadratically in the worst case.逻辑单元的并行设计逻辑单元的并行设计2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理2121Transistor sizing as long as fan-out capacitance dominatesProgressive sizingInNCLC3C2C1In1In2In3M

12、1M2M3MNDistributed RC lineM1 M2 M3 MN (the fet closest to the output is the smallest) Can reduce delay by more than 20%; decreasing gains as technology shrinks逻辑单元的并行设计逻辑单元的并行设计2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理Transistor orderingC2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CLcritical pathcritical path

13、charged101chargedcharged1delay determined by time to discharge CL, C1 and C2delay determined by time to discharge CL1101chargeddischargeddischarged逻辑单元的并行设计逻辑单元的并行设计 通过合理设计，减少发生状态变化的单元数量通过合理设计，减少发生状态变化的单元数量2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理组合逻辑优化组合逻辑优化2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理NiiiifgpDe

14、lay1For given N: Ci+1/Ci = Ci/Ci-1To find N: Ci+1/Ci 4How to generalize this to any logic path?CLInOut12N(in units of t tinv)2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理逻辑努力逻辑努力1LunitunitinCDelayk RCpg fCtp intrinsic delay (RunitCunit)g logical effort f effective fanoutNormalize everything to an inverter:gi

15、nv =1, pinv = 1Divide everything by t tinv(everything is measured in unit delays t tinv)Assume = 1.2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理组合逻辑延迟组合逻辑延迟Gate delay:d = h + peffort delayintrinsic delayEffort delay:h = g flogical efforteffective fanout = Cout/CinLogical effort is a function of topology, ind

16、ependent of sizingEffective fanout (electrical effort) is a function of load/gate size2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理Logical effort is the ratio of input capacitance of a gate to the inputcapacitance of an inverter with the same output currentg = 1g = 4/3g = 5/3BAABFVDDVDDABABFVDDAAF1222221144I

17、nverte r2-input N A N D2-input N O R分支努力分支努力2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理Branching effort: pathonpathoffpathonCCCb2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理Stage effort: hi = gifiPath electrical effort: F = Cout/CinPath logical effort: G = g1g2gNBranching effort: B = b1b2bNPath effort: H = GFBPath

18、delay: D = S Sdi = S Spi + S ShiNiiiifgpDelay12.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理HhNWhen each stage bears the same effort:NHh PNHpfgDNiii/1Minimum path delayEffective fanout of each stage:iighf Stage efforts: g1f1 = g2f2 = = gNfN2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理For a given load, and given input capacitance of the first gateFind optimal number of stages and optimal sizinginvNNpNHD/1NHh/1Substitute best stage effort2.4 2.4 动态分析：延迟时间及缓冲处理动态分析：延迟时间及缓冲处理1abc5g = 1f = ag = 5/3f = b/ag = 5/3f = c/bg = 1f = 5/cEffective fanout, F = 5G = 25/9H = 125/9 =