智能洗衣机程序

1、/=washer.v=/ moduleModuleWasher(State,Mode,Second,Beep,CP,nCR,En,ModeCh,Fullpro,Rinse,Dehy,500hz,S);Input CP,nCR,En,ModeCh,FullPro,Rinse,Dehy,500hz,S;Output7:0Second;Output3:0State,mode;Output Beep;Reg7:0Second;Reg3:0State,Mode;Reg Beep;Reg ModeEnd;Wire Mode En;wire veryEn,dirtyEn,normEn,rinseEn,deh

2、yEn,fModeEn,rModeEn,dModeEn;wire Stop;supply1 Vdd;reg3:0State1,State2,State3,State4,State5,State6,State7,State8; reg7:0Second1,Second2,Second3,Second4,Second5,Second6,Second7,Second8;regcountEnd,countEnd1,countEnd2,countEnd3,countEnd4,countEnd5,countEnd6,countEnd7,countEnd8;/*模式选择*/*单选模式*/ assign as

3、sign Mode_En=Vdd&&(En); count5asc U1(Mode,ModeEnd,nCR,Mode_En,ModeCh);veryEn=Vdd&&En&&(Stop)&&(FullPro)&&(Rinse)&&(Dehy)&&(Mode=4'b0001)&&S;assigndirtyEn=Vdd&&En&&(Stop)&&(FullPro)&&(Rinse)&&(

4、Dehy)&&(Mode=4'b0010)&&S;assignnormEn=Vdd&&En&&(Stop)&&(FullPro)&&(Rinse)&&(Dehy)&&(Mode=4'b0011)&&S;assignrinseEn=Vdd&&En&&(Stop)&&(FullPro)&&(Rinse)&&(Dehy)&&(Mode=4'

5、b0100)&&S;assigndehyEn=Vdd&&En&&(Stop)&&(FullPro)&&(Rinse)&&(Dehy)&&(Mode=4'b0101);/*组合模式*/ assign verydirty U2(State1,Second1,countEnd1,CP,nCR,veryEn);/模式1 dirty U3(State2,Second2,countEnd2,CP,nCR,dirtyEn); /模式2 normal U4(State3,Second3,co

6、untEnd3,CP,nCR,normEn); /模式3 rinse U5(State4,Second4,countEnd4,CP,nCR,rinseEn); /模式4 dehydration U6(State5,Second5,countEnd5,CP,nCR,dehyEn); /模式5fModeEn=Vdd&&En&&(Stop)&&(FullPro)&&(Rinse)&&(Dehy)&&(Mode>=4'b0001&&Mode<=4'b0011);a

7、ssignrModeEn=Vdd&&En&&(Stop)&&(FullPro)&&(Rinse)&&(Dehy)&&(Mode=4'b0100);assigndModeEn=Vdd&&En&&(Stop)&&(FullPro)&&(Rinse)&&(Dehy)&&(Mode>=4'b0101);/*选择切换模块*/ always(veryEn or dirtyEn or normEn

8、 or rinseEn or dehyEn or fModeEn full U7(State6,Second6,countEnd6,CP,nCR,fModeEn,Mode,S);/全过程 RinseMode U8(State7,Second7,countEnd7,CP,nCR,rModeEn,S);/漂洗模式 dehydration U9(State8,Second8,countEnd8,CP,nCR,dModeEn);/脱水模式 or rModeEn or dModeEn or nCR or countEnd)begin if(veryEn) begin Second<=Second1

9、;State<=State1;countEnd<=countEnd1; end if(dirtyEn) begin Second<=Second2; State<=State2; countEnd<=countEnd2; end if(normEn) begin Second<=Second3; State<=State3; countEnd<=countEnd3; end if(rinseEn) begin Second<=Second4; State<=State4; countEnd<=countEnd4; end if(

10、dehyEn) begin Second<=Second5; State<=State5; countEnd<=countEnd5; end if(fModeEn)begin Second<=Second6; State<=State6; countEnd<=countEnd6; end if(rModeEn) begin Second<=Second7; State<=State7; countEnd<=countEnd7; end if(dModeEn) begin Second<=Second8; State<=State

11、8; countEnd<=countEnd8; end if(nCR) begin Second<=8'h00; State<=4'b0000; countEnd<=1'b0; end if(countEnd=1'b1) begin Second<=8'h00; State<=4'b0000; end end /*蜂鸣器模块*/ Beeper U10(Beep,CP,nCR,countEnd,_500hz); /*终止模块*/ assign Stop=countEnd;endmodule/= verydirty

12、.v=/ module verydirty(State,Second,countEnd,CP,nCR,En);input CP,nCR,En;output3:0State;output7:0Second;output countEnd;reg3:0State;reg7:0Second;reg countEnd;count30U1(Second7:4,Se；always(posedgeCP)；if(En)；begin；State<=4'b0001;；end；endmodule；/=；inputCP,nCR,En;；output3:0State;；output7:0Second;；o

13、utputco_count30 U1(Second7:4,Second3:0,countEnd,nCR,En,CP);always(posedge CP)if(En)beginState<=4'b0001;endendmodule/= dirty.v=/ module dirty(State,Second,countEnd,CP,nCR,En);input CP,nCR,En;output3:0State;output7:0Second;output countEnd;reg3:0State;reg7:0Second;reg countEnd;count20 U1(Second7

14、:4,Second3:0,countEnd,nCR,En,CP);always(posedge CP)if(En)beginState<=4'b0010;endendmodule/= normal.v=/ module normal(State,Second,countEnd,CP,nCR,En);input CP,nCR,En;output3:0State;output7:0Second;output countEnd;reg3:0State;reg7:0Second;reg countEnd;count10 U1(Second3:0,countEnd,nCR,En,CP);a

15、lways(posedge CP)if(En)beginState<=4'b0011;Second7:4<=4'b0000;endendmodule/= rinse.v=/ module rinse(State,Second,countEnd,CP,nCR,En);input CP,nCR,En;output3:0State;output7:0Second;output countEnd;reg3:0State;reg7:0Second;reg countEnd;count5 U1(Second3:0,countEnd,nCR,En,CP);always(En)if

16、(En)beginState<=4'b0100;Second7:4<=4'b0000;endendmodule/= dehydration.v=/ module dehydration(State,Second,countEnd,CP,nCR,En);input CP,nCR,En;output3:0State;output7:0Second;output countEnd;reg3:0State;reg7:0Second;reg countEnd;count3 U1(Second3:0,countEnd,nCR,En,CP);always(En)beginSeco

17、nd7:4<=4'b0000;if(En)|(countEnd=1'b1)beginState<=4'b0000;endelse if(Second>8'b00000000)beginState<=4'b0101;endendendmodule/= full.v=/ module full(State,Second,countEnd,CP,nCR,En,Mode,S);input CP,nCR,En,S;input3:0Mode;output3:0State;output7:0Second;output countEnd;reg3

18、:0State;reg7:0Second,Second1,Second2,Second3;reg countEnd,countEnd1,countEnd2,countEnd3;reg flag;wire comEn1;wire comEn2;wire comEn3;wire Vdirty_En,dirty_En,norm_En;supply1 Vdd;assign Vdirty_En=Vdd&&(Mode=4'b0001);assign dirty_En=Vdd&&(Mode=4'b0010);assign norm_En=Vdd&&am

19、p;(Mode=4'b0011);count49 U1(Second17:4,Second13:0,countEnd1,nCR,comEn1,CP); count39 U2(Second27:4,Second23:0,countEnd2,nCR,comEn2,CP); count29 U3(Second37:4,Second33:0,countEnd3,nCR,comEn3,CP);always(Vdirty_En or dirty_En or norm_En)beginif(Vdirty_En)begin Second<=Second1;countEnd<=countEn

20、d1; endif(dirty_En)begin Second<=Second2;countEnd<=countEnd2; endif(norm_En)begin Second<=Second3;countEnd<=countEnd3; endendalways(Second)beginif(countEnd=1'b1)begin；State<=4'b0000;；end；elseif(Second>8'b；State<=4'b0001;；elseif(Second>8'b；State<=4'b

21、0010;；elseif(Second>8'b；State<=4'b0011;；els_beginState<=4'b0000;endelse if(Second>8'b00011000&&comEn1)State<=4'b0001;else if(Second>8'b00011000&&comEn2)State<=4'b0010;else if(Second>8'b00011000&&comEn3)State<=4'b0

22、011;else if(Second<=8'b00011000&&Second>8'b00010101)|(Second<=8'b00010000&&Second>8'b00000111)|(Second<=8'b00000010&&Second>=8'b00000000)State<=4'b0101;elseState<=4'b0100;endalways(posedge CP or posedge S or negedge nCR)

23、beginif(nCR)flag<=1'b0;else if(S)flag<=1'b1;else if(Second=8'b00010110)|(Second=8'b00001000)flag<=1'b0;elseflag<=flag;endassign comEn1=Vdirty_En&&flag&&En;assign comEn2=dirty_En&&flag&&En;assign comEn3=norm_En&&flag&&En;

24、endmodule/= RinseMode.v=/ module RinseMode(State,Second,countEnd,CP,nCR,En,S);input CP,nCR,En,S;output3:0State;output7:0Second;output countEnd;reg3:0State;reg7:0Second;reg countEnd;reg flag;wire comEn;count16 U5(Second7:4,Second3:0,countEnd,nCR,comEn,CP);always(Second)beginif(countEnd=1'b1) begi

25、n State<=4'b0000; endelseif(Second<=8'b00010110&&Second>=8'b00010001)|(Second<8'b00001000&&Second>=8'b00000011)beginState<=4'b0100;endelsebeginState<=4'b0101;endendalways(posedge CP or posedge S or negedge nCR)beginif(nCR)flag<=1

26、9;b0;else if(S)flag<=1'b1;else if(Second=8'b00010110)|(Second=8'b00001000)flag<=1'b0;endassign comEn=En&&flag;endmodule/= Beeper.v=/ module Beeper(alarm,CP,nCR,BeepEn,_500hz);input _500hz,CP,nCR,BeepEn;output alarm;reg EndS;reg 3:0Q;supply1 Vdd;count2 U1(Q,EndS,nCR,Beep

27、En,CP);assign alarm=BeepEn&&_500hz&&(EndS);endmodule/= count49.v=/ module count49(CntH,CntL,EndS,nCR,EN,CP);input CP,nCR,EN;output3:0CntH,CntL;output EndS;reg EndS;reg 3:0CntH,CntL;always(posedge CP or negedge nCR)beginif(nCR) CntH,CntL<=8'h48; else if(EN) CntH,CntL<=CntH,C

28、ntL; else if(CntH<0)|(CntL<0)|(CntH=0)&&(CntL<=0) ) begin EndS<=1'b1; end else if(CntH=1)&&(CntL>0)begin CntH<=CntH; CntL<=CntL-1'b1; end else if(CntH=2)&&(CntL>0) begin CntH<=CntH; CntL<=CntL-1'b1; end else if(CntH=3)&&(CntL&

29、gt;0) begin CntH<=CntH; CntL<=CntL-1'b1; end else if(CntH=4)&&(CntL>0) begin CntH<=CntH; CntL<=CntL-1'b1; end else if (CntL=0) begin CntH<=CntH-1'b1; CntL<=4'b1001; end else begin CntH<=CntH; CntL<=CntL-1'b1; endendendmodule/= count39.v=/ module

30、 count39(CntH,CntL,EndS,nCR,EN,CP);input CP,nCR,EN;output3:0CntH,CntL;output EndS;reg EndS;reg 3:0CntH,CntL;always(posedge CP or negedge nCR)beginif(nCR) CntH,CntL<=8'h38;elseif(CntH<0)|(Cnt；end；endmodule；/=；inputCP,nCR,EN;；output3:0CntH,CntL;；outputEndS;；regEndS;；reg3:0CntH,CntL;；always(p

31、osedgeCPorneged；begin；elseif(_else if(CntH<0)|(CntL<0)|(CntH=0)&&(CntL<=0) ) begin EndS<=1'b1; end else if(CntH=1)&&(CntL>0) begin CntH<=CntH; CntL<=CntL-1'b1; end else if(CntH=2)&&(CntL>0) begin CntH<=CntH; CntL<=CntL-1'b1; end else

32、if(CntH=3)&&(CntL>0) begin CntH<=CntH; CntL<=CntL-1'b1; end else if (CntL=0) begin CntH<=CntH-1'b1; CntL<=4'b1001; end else begin CntH<=CntH; CntL<=CntL-1'b1; endendendmodule/= count30.v=/ module count30(CntH,CntL,EndS,nCR,EN,CP);input CP,nCR,EN;output3:0

33、CntH,CntL;output EndS;reg EndS;reg 3:0CntH,CntL;always(posedge CP or negedge nCR)beginelse if(EN) CntH,CntL<=CntH,CntL; else if(CntH<0)|(CntL<0)|(CntH=0)&&(CntL<=0) ) begin EndS<=1'b1; end else if(CntH=1)&&(CntL>0) begin CntH<=CntH; CntL<=CntL-1'b1; en

34、d else if(CntH=2)&&(CntL>0) begin CntH<=CntH; CntL<=CntL-1'b1; end else if(CntH=3)&&(CntL>0) begin CntH<=CntH; CntL<=CntL-1'b1; end else if(CntH=4)&&(CntL>0) begin CntH<=CntH; CntL<=CntL-1'b1; end else if (CntL=0) begin CntH<=CntH-1&#

35、39;b1; CntL<=4'b1001; end else begin CntH<=CntH; CntL<=CntL-1'b1; endendendmodule/= count29.v=/ module count29(CntH,CntL,EndS,nCR,EN,CP);input CP,nCR,EN;output3:0CntH,CntL;output EndS;reg EndS;reg 3:0CntH,CntL;always(posedge CP or negedge nCR)beginendendmodule/= count20.v=/ module c

36、ount20(CntH,CntL,EndS,nCR,EN,CP);input CP,nCR,EN;output3:0CntH,CntL;output EndS;reg EndS;reg 3:0CntH,CntL; if(nCR) CntH,CntL<=8'h28; else if(EN) CntH,CntL<=CntH,CntL; else if(CntH<0)|(CntL<0)|(CntH=0)&&(CntL<=0) ) begin EndS<=1'b1; end else if(CntH=1)&&(CntL

37、>0) begin CntH<=CntH; CntL<=CntL-1'b1; end else if(CntH=2)&&(CntL>0) begin CntH<=CntH; CntL<=CntL-1'b1; end else if (CntL=0) begin CntH<=CntH-1'b1; CntL<=4'b1001; end else begin CntH<=CntH; CntL<=CntL-1'b1; endalways(posedge CP or negedge nCR

38、)beginendendmodule/= count16.v=/ module count16(CntH,CntL,EndS,nCR,EN,CP);input CP,nCR,EN; if(nCR) CntH,CntL<=8'h19; else if(EN) CntH,CntL<=CntH,CntL; else if(CntH<0)|(CntL<0)|(CntH=0)&&(CntL<=0) ) begin EndS<=1'b1; end else if(CntH=1)&&(CntL>0) begin Cnt

39、H<=CntH; CntL<=CntL-1'b1; end else if(CntH=2)&&(CntL>0) begin CntH<=CntH; CntL<=CntL-1'b1; end else if(CntH=3)&&(CntL>0) begin CntH<=CntH; CntL<=CntL-1'b1; end else if(CntH=4)&&(CntL>0) begin CntH<=CntH; CntL<=CntL-1'b1; end el

40、se if (CntL=0) begin CntH<=CntH-1'b1; CntL<=4'b1001; end else begin CntH<=CntH; CntL<=CntL-1'b1; endoutput3:0CntH,CntL;output EndS;reg EndS;reg 3:0CntH,CntL;always(posedge CP or negedge nCR)beginendendmodule/= count10.v=/ module count10(Q,EndS,nCR,EN,CP);input CP,nCR,EN;outpu

41、t 3:0Q;output EndS; if(nCR) CntH,CntL<=8'h15; else if(EN) CntH,CntL<=CntH,CntL; else if(CntH<0)|(CntL<0)|(CntH=0)&&(CntL<=0) ) begin EndS<=1'b1; end else if(CntH=1)&&(CntL>0) begin CntH<=CntH; CntL<=CntL-1'b1; end else if (CntL=0) begin CntH<=CntH-1'b1; CntL<=4'b1001; end else begin CntH<=CntH; CntL<=CntL-1'b1; endreg3:0Q;；regEndS;；always(posedgeCPorneged；begin；if(nCR)；begin；EndS<=1'b0;；Q<=4'b1010;；end；elseif(EN)Q<=Q;；elseif(Q=4'b0000)；begin；EndS<=1'b1;；end；_reg 3:0 Q;reg EndS;a