eda期中试卷A及答案

1、2A用Q1,Q2,D信号要好些。未标信号扣5分 D<= X or Q1; 放在时钟上升沿里扣5分4A. 信号用counter好些用变量或信号，用integer或std_logic_vector型3A. 图最好选用答案的图用变量或信号，用integer或std_logic_vector型6A.实体名不允许为JKFFIf prn写在外面扣5分 or 写成加号扣5分7A: 程序 A B赋高阻5分, A<=B, B<=A, 无分 图10分.1A.简述信号与变量的区别。(至少列举5个)答案：1 赋值符号不同 信号用 <= 变量用 :=2 功能不同 信号常常是物理硬件的节点 变量用

2、来描述算法3 信号是全局量，用于结构体，实体，块中 变量是局部量，用于进程，函数，子程序4 信号的赋值需要有延时 变量是立即赋值 5 进程中的敏感表只能是信号2A. 用VHDL描述下面电路图。(实体名用cir1)答案：library IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CIR1 IS PORT ( X, CLK : IN STD_LOGIC;Y : OUT STD_LOGIC);END ;ARCHITECTURE ONE OF CIR1 ISSIGNAL A, B, C: std_logic;BEGINB <= not (X OR A) ;PR

3、OCESS (CLK)BEGINIF CLK'EVENT AND CLK = '1' THENA <= C ;C <= B;END IF;END PROCESS;Y <= C;END ONE;3A. 频率计控制电路的工作波形如图所示，试用VHDL设计该电路。(注意时钟信号的下降沿有效) (实体名用tfctrl)答案:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity tfctrl isport(clk:in std_logic;en,lock,c

4、lear: out std_logic);end ;architecture bhv of tfctrl issignal temp: std_logic_vector(3 downto 0);beginprocess(clk) begin if falling_edge(clk) then if temp<15 then temp<=temp+1; else temp<="0000"end if;if temp<8 then en<='1' else en<='0'end if;if temp=9 the

5、n lock<='1' else lock<='0'end if;if temp=13 then clear<='1' else clear<='0'end if; end if;end process;end ;答案2: 用case语句library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity tfctrl isport(clk:in std_logic;en,lock,clear: out std_log

6、ic);end ;architecture bhv of tfctrl issignal temp: integer range 15 downto 0;beginprocess(clk) begin if falling_edge(clk) then if temp<15 then temp<=temp+1; else temp<=0;end if;case temp iswhen 0 to 7 => en<='1' lock<='0' clear<='0' when 9 => en<=&#

7、39;0' lock<='1' clear<='0' when 13 => en<='0' lock<='0' clear<='1' when others => en<='0' lock<='0' clear<='0' end case; end if;end process;end ;4A. 试用VHDL设计一个六分频电路，要求50%的占空比。（输入clk，输出Q,实体名用divn）答案：libr

8、ary ieee;use ieee.std_logic_1164.all;entity divn is port(clk:in std_logic; Q:out std_logic); end;architecture behav of divn issignal Q1: std_logic; signal Q2: std_logic; beginprocess(clk) variable a: integer range 0 to 2; begin if clk'event and clk='1' thenif a=2 then a:=0;Q1<='1&

9、#39; else a:=a+1;Q1<='0' end if; end if;end process;process(Q1) begin if Q1'event and Q1='1' thenQ2<=not Q2; end if;end process;Q<=Q2 ;end;答案2：library ieee;use ieee.std_logic_1164.all;entity divn is port(clk:in std_logic; Q:out std_logic); end;architecture behav of divn

10、issignal Q1: std_logic; beginprocess(clk) variable a: integer range 0 to 5; begin if clk'event and clk='1' thenif a=5 then a:=0; else a:=a+1; end if; if a<3 then Q1<='1' else Q1<='0' end if; end if;end process;Q<=Q1 ;end;答案2（用信号）(并且分成两进程)library ieee;use ieee.

11、std_logic_1164.all;entity divn is port(clk:in std_logic; Q:out std_logic); end;architecture behav of divn issignal Q1: std_logic; signal Q2: std_logic; signal a: integer range 0 to 5; beginprocess(clk,a) begin if clk'event and clk='1' thenif a<5 then a<=a+1; else a<=0; end if; e

12、nd if;end process;process(clk,a) begin if clk'event and clk='1' thenif a<3 then Q1<='1' else Q1<='0' end if; end if;end process;Q<=Q1 ;end;答案3: library ieee;use ieee.std_logic_1164.all;entity divn is port(clk:in std_logic; Q:out std_logic); end;architecture be

13、hav of divn issignal Q1: std_logic; beginprocess(clk) variable a: integer range 0 to 5; begin if clk'event and clk='1' thenif a=5 then a:=0; Q1<='0'elsif a<3 then a:=a+1; Q1<='1'else a:=a+1; Q1<='0'end if; end if;end process;Q<=Q1 ;end;答案4:library i

14、eee;use ieee.std_logic_1164.all;entity divn is port(clk:in std_logic; Q:out std_logic); end;architecture behav of divn issignal Q1: std_logic; beginprocess(clk) variable a: integer range 0 to 2; begin if clk'event and clk='1' thenif a=2 then a:=0; Q1<=not Q1;else a:=a+1;end if; end if

15、;end process;Q<=Q1 ;end;答案5:library ieee;use ieee.std_logic_1164.all;entity divn is port(clk:in std_logic; Q:out std_logic); end;architecture behav of divn issignal Q1: std_logic; beginprocess(clk) variable a: integer range 0 to 5; begin if clk'event and clk='1' then a:=a+1;if a=3 the

16、n a:=0; Q1<=not Q1; end if; end if;end process;Q<=Q1 ;end;答案6： library ieee;use ieee.std_logic_1164.all;entity divn is port(clk:in std_logic; Q:out std_logic); end;architecture behav of divn issignal Q1: std_logic; beginprocess(clk) variable a: integer range 0 to 5; begin if clk'event and

17、clk='1' then a:=a+1;if a=1 then Q1<='1' end if;if a=4 then Q1<='0' end if;if a=6 then a:=0; end if; end if;end process;Q<=Q1 ;end;5A. 试用VHDL设计一个带进位输入和进位输出的8位加法器。（请直接用std_logic_unsigned 程序包中的加法运算符。） 已知实体部分为：entity adder8 is port(cin: in std_logic; A,B: in std_logic_ve

18、ctor(7 downto 0); S: out std_logic_vector(7 downto 0); cout: out std_logic);end adder8;答案：function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is constant length: INTEGER := maximum(L'length, R'length); variable result : STD_LOGIC_VECTOR (length-1 downto 0

19、);begin result := UNSIGNED(L) + UNSIGNED(R); return std_logic_vector(result);end; function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is variable result : STD_LOGIC_VECTOR (L'range); begin result := UNSIGNED(L) + R; return std_logic_vector(result);end;library ieee;u

20、se ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder8 is port(cin: in std_logic; A,B: in std_logic_vector(7 downto 0); S: out std_logic_vector(7 downto 0); cout: out std_logic);end adder8;architecture one of adder8 is signal stemp: std_logic_vector(8 downto 0);begin stemp<= (&#

21、39;0'&A)+('0'&B)+cin; -或 stemp<= ('0'&A)+('0'&B)+ "0000000"+cin; -或 stemp<= ('0'&A)+ B +cin; -或 stemp<= "00000000"+A+ B +cin; S<= stemp(7 downto 0); cout<=stemp(8);end one;说明：stemp<= A+B+cin在maxplus中通过，但qua

22、rtus中不行,提示位数不对6A. 用VHDL描述一个JK触发器，其中时钟信号CLK上升沿有效。PRN是异步置位端，低电平有效。CLRN是异步清零端，低电平有效。已知JK触发器的特征方程为(实体名用JKFF)答案：用变量实现LIBRARY ieee;USE ieee.std_logic_1164.all; ENTITY JKFF IS port(J,K,PRN,CLRN,CLK : IN STD_LOGIC;Q : OUT STD_LOGIC);END JKFF;ARCHITECTURE behave OF JKFF IS BEGIN process(CLK,CLRN,PRN)variable

23、 Q1 : STD_LOGIC;beginif (CLRN = '0') thenQ1 := '0'elsif (PRN = '0') thenQ1 := '1'elsif (rising_edge(CLK) thenQ1 := (NOT(Q1) AND J) OR (Q1 AND (NOT(K);end if;Q <= Q1;end process;END;也可用信号实现LIBRARY ieee;USE ieee.std_logic_1164.all; ENTITY JKFF IS port(J,K,PRN,CLRN,CL

24、K : IN STD_LOGIC;Q : OUT STD_LOGIC);END JKFF;ARCHITECTURE behave OF JKFF IS signal Q1 : STD_LOGIC;BEGIN process(CLK,CLRN,PRN)beginif (CLRN = '0') thenQ1 <= '0'elsif (PRN = '0') thenQ1 <= '1'elsif (rising_edge(CLK) thenQ1 <= (NOT(Q1) AND J) OR (Q1 AND (NOT(K);end if;Q <= Q1;end process;END;7A. 试用VHDL设计1位二进制数据收发器，并画出综合器可能综合出的电路图。EN是使能控制端，当EN=0时电路工作，EN=1时