数字逻辑考前搞懂作业题并且速成就够了乱七八糟的未6图

1、 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.1 Logic symbol for a half-adder. Open file F06-01 to verify operation. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle Rive

2、r, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.2 Half-adder logic diagram. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.3 Logic sym

3、bol for a full-adder. Open file F06-03 to verify operation. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.4 Full-adder logic. Open file F06-04 to verify operation. Copyright 2009 by P

4、earson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.5 Full-adder implemented with half-adders. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital F

5、undamentals, Tenth EditionThomas L. FloydFigure 6.6 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.7 Block diagram of a basic 2-bit parallel adder using two full-adders. Open file F06-

6、07 to verify operation. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.8 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital

7、 Fundamentals, Tenth EditionThomas L. FloydFigure 6.9 A 4-bit parallel adder. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.10 Four-bit parallel adder. Copyright 2009 by Pearson Highe

8、r Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.11 Propagation delay characteristics for the 74LS283. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fu

9、ndamentals, Tenth EditionThomas L. FloydFigure 6.12 Examples of adder expansion. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.13 Two 74LS283 adders connected as an 8-bit parallel add

10、er (pin numbers are in parentheses). Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.14 A voting system using full-adders and parallel binary adders. Copyright 2009 by Pearson Higher Ed

11、ucation, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.15 A 4-bit parallel ripple carry adder showing “worst-case” carry propagation delays. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458Al

12、l rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.16 Illustration of conditions for carry generation and carry propagation. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L.

13、FloydFigure 6.17 Carry generation and carry propagation in terms of the input bits to a 4-bit adder. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.18 Logic diagram for a 4-stage look-

14、ahead carry adder. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.19 Basic comparator operation. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All

15、 rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.20 Logic diagram for equality comparison of two 2-bit numbers. Open file F06-20 to verify operation. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamental

16、s, Tenth EditionThomas L. FloydFigure 6.21 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.22 Logic symbol for a 4-bit comparator with inequality indication. Copyright 2009 by Pearson H

17、igher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.23 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure

18、6.24 Pin diagram and logic symbol for the 74LS85 4-bit magnitude comparator (pin numbers are in parentheses). Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.25 An 8-bit magnitude compa

19、rator using two 74LS85s. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.26 Decoding logic for the binary code 1001 with an active-HIGH output. Copyright 2009 by Pearson Higher Educatio

20、n, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.27 Decoding logic for producing a HIGH output when 1011 is on the inputs. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.

21、Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.28 Logic symbol for a 4-line-to-16-line (1-of-16) decoder. Open file F06-28 to verify operation. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThoma

22、s L. FloydFigure 6.29 Pin diagram and logic symbol for the 74HC154 1-of-16 decoder. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.30 A 5-bit decoder using 74HC154s. Copyright 2009 by

23、Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.31 A simplified computer I/O port system with a port address decoder with only four address lines shown. Copyright 2009 by Pearson Higher Education, Inc.Up

24、per Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.32 The 74HC42 BCD-to-decimal decoder. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L.

25、FloydFigure 6.33 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.34 Logic symbol for a BCD-to-7-segment decoder/driver with active-LOW outputs. Open file F06-34 to verifyoperation. Copy

26、right 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.35 Pin diagram and logic symbol for the 74LS47 BCD-to-7-segment decoder/driver. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle

27、River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.36 Examples of zero suppression using the 74LS47 BCD to 7-segment decoder/driver. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fund

28、amentals, Tenth EditionThomas L. FloydFigure 6.37 Logic symbol for a decimal-to-BCD encoder. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.38 Basic logic diagram of a decimal-to-BCD e

29、ncoder. A 0-digit input is not needed because the BCD outputs are all LOW when there are no HIGH inputs. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.39 Pin diagram and logic symbol

30、for the 74HC147 decimal-to-BCD priority encoder (HPRI means highest value input has priority). Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.40 Logic symbol for the 74LS148 8-line-to-

31、3-line encoder. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.41 A 16-line-to-4 line encoder using 74LS148s and external logic. Copyright 2009 by Pearson Higher Education, Inc.Upper S

32、addle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.42 A simplified keyboard encoder. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigu

33、re 6.43 Four-bit binary-to-Gray conversion logic. Open file F06-43 to verify operation. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.44 Four-bit Gray-to-binary conversion logic. Open

34、 file F06-44 to verify operation. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.45 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reser

35、ved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.46 Logic symbol for a 1-of-4 data selector/multiplexer. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.47 Logic diagram f

36、or a 4-input multiplexer. Open file F06-47 to verify operation. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.48 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, Ne

37、w Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.49 Pin diagram and logic symbol for the 74HC157 quadruple 2-input data selector/multiplexer. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fu

38、ndamentals, Tenth EditionThomas L. FloydFigure 6.50 Pin diagram and logic symbol for the 74LS151 8-input data selector/multiplexer. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.51 A

39、16-input multiplexer. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.52 Simplified 7-segment display multiplexing logic. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle Ri

40、ver, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.53 Data selector/multiplexer connected as a 3-variable logic function generator. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundame

41、ntals, Tenth EditionThomas L. FloydFigure 6.54 Data selector/multiplexer connected as a 4-variable logic function generator. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.55 A 1-line-

42、to-4-line demultiplexer. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.56 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digit

43、al Fundamentals, Tenth EditionThomas L. FloydFigure 6.57 The 74HC154 decoder used as a demultiplexer. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.58 Copyright 2009 by Pearson Higher

44、 Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.59 The 74LS280 9-bit parity generator/checker. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamenta

45、ls, Tenth EditionThomas L. FloydFigure 6.60 Simplified data transmission system with error detection. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.61 Example of data transmission wit

46、h and without error for the system in Figure 660. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.62 Decoder waveforms with output glitches. Copyright 2009 by Pearson Higher Education,

47、Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.63 Decoder waveform displays showing how transitional input states produce glitches in the outputwaveforms. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New J

48、ersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.64 Application of a strobe waveform to eliminate glitches on decoder outputs. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth

49、EditionThomas L. FloydFigure 6.65 Timing requirements for the traffic signals. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.66 State diagram for the traffic signal control. Copyright

50、 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.67 Block diagram of the traffic signal control system. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rig

51、hts reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.68 Block diagram of the combinational logic portion of the system. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure

52、6.69 State decoder logic. Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.70 Multisim circuit screen for the combinational logic showing the first state. Copyright 2009 by Pearson Highe

53、r Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.71 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.72

54、 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.73 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth E

55、ditionThomas L. FloydFigure 6.74 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.75 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserv

56、ed.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.76 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.77 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, N

57、ew Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.78 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.79 Copyright 2009 by Pearson Higher Educ

58、ation, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.80 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.81 Copyr

59、ight 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.82 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth Edition

60、Thomas L. FloydFigure 6.83 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Digital Fundamentals, Tenth EditionThomas L. FloydFigure 6.84 Copyright 2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Dig