基于FPGA的Verilog HDL数字钟设计 -

1、基于FPGA的Verilog HDL数字钟设计专业班级 姓 名 学 号 一、实验目的1.掌握可编程逻辑器件的应用开发技术 设计输入、编译、仿真和器件编程；2.熟悉一种EDA软件使用；3.掌握Verilog设计方法； 4.掌握分模块分层次的设计方法； 5.用Verilog完成一个多功能数字钟设计; 6.学会FPGA的仿真。二、实验要求² 功能要求：利用实验板设计实现一个能显示时分秒的多功能电子钟，基本功能：1) 准确计时，以数字形式显示时、分、秒，可通过按键选择当前显示时间范围模式；2) 计时时间范围 00:00:0023:59:593) 可实现

2、校正时间功能；4) 可通过实现时钟复位功能：00:00:00扩展功能：5) 定时报：时间自定(不要求改变)，闹1分钟(1kHz)-利用板上LED或外接电路实现。6) 仿广播电台正点报时：XX:59:51,53,55,57(500Hz);59(1kHz) -用板上LED或外接7) 报整点时数：XX:00:00.5-XX.5(1kHz)，自动、手动-用板上LED或外接8) 手动输入校时；9) 手动输入定时闹钟；10) 万年历；11) 其他扩展功能；² 设计步骤与要求：1) 计算并说明采用Basys2实验板时钟50MHz实现系统功能的基本原理。2) 在Xilinx ISE13.1 软件中，

3、利用层次化方法，设计实现模一百计数及显示的电路系统，设计模块间的连接调用关系，编写并输入所设计的源程序文件。3) 对源程序进行编译及仿真分析（注意合理设置，以便能够在验证逻辑的基础上尽快得出仿真结果）。4) 输入管脚约束文件，对设计项目进行编译与逻辑综合，生成下载所需.bit文件。5) 在Basys2实验板上下载所生成的.bit文件，观察验证所设计的电路功能。3、 实验设计功能说明：实现时钟，时间校时，闹铃定时，秒表计时等功能1. 时钟功能：完成分钟/小时的正确计数并显示；秒的显示用LED灯的闪烁做指示；时钟利用4位数码管显示时分；2. 闹钟定时：实现定时提醒及定时报时，利用LED灯代替扬声器

4、发出报时声音；3. 时钟校时：当认为时钟不准确时，可以分别对分钟和小时位的值进行调整；4. 秒表功能：利用4个数码管完成秒表显示： 可以实现清零、暂停并记录时间等功能。秒表利用4位数码管计数；方案说明：本次设计由时钟模块和译码模块组成。时钟模块中50MHz的系统时钟clk分频产生一个1Hz的使能控制信号enable，并以此产生1s的脉冲second_en以实现每秒计时，控制各个模式下的计数显示。由模式控制信号选择当前数码管显示哪个状态：mode=00，时钟常规显示状态，mode=01，闹铃定时状态，mode=10，时钟校时状态，mode=11，秒表计时状态；时钟：利用count，smin0，s

5、min1，shour0，shour1的计数来实现，具体情况见程序； 校时：当turn=1时，调整分位smin1、smin0；当turn=0时，调整小时位shour1、shour0；闹铃：当turn=1时，调整分位amin1、amin0；当turn=0时，调整小时位ahour1、ahour0；秒表：当pause=0时，开始计时；当pause=1时，暂停。4、 实验代码时钟模块module clock(clk, clr, pause, turn, mode, sec, min1, min0, hour1, hour0, alert, LD_alert );input clk; /时钟信号(50MH

6、z)input clr; /清零键input pause; /秒表暂停键input turn; /调整分还是小时位的控制input 1:0mode; /决定时钟显示功能状态output sec; /接发光二极管output 3:0min1; /用于输出接数码管4output 3:0min0; /用于输出接数码管3output 3:0hour1; /用于输出接数码管2output 3:0hour0; /用于输出接数码管1output alert; /接发光二极管，代替蜂鸣器output LD_alert; /当闹铃设定后，发光二极管显示wire sec; /秒位显示wire LD_alert;

7、/用于闹铃存在时的提醒显示/wire clk1; /时钟1s/wire clk2; /时钟100ms，用于秒表最小计时单位/wire clr1;reg 3:0min1; /常规显示reg 3:0min0; /常规显示reg 3:0hour1; /常规显示reg 3:0hour0; /常规显示reg 3:0smin1; /校时reg 3:0smin0; /校时reg 3:0shour1; /校时reg 3:0shour0; /校时reg 3:0amin1; /闹铃reg 3:0amin0; /闹铃reg 3:0ahour1; /闹铃reg 3:0ahour0; /闹铃reg 3:0mmin1;

8、/秒表reg 3:0mmin0; /秒表reg 3:0mhour1; /秒表reg 3:0mhour0; /秒表reg alert; /当闹铃到时高电平输出reg 7:0count;reg 24:0counter;reg enable;reg en1,en2;wire second_en;always (posedge clk) /generate 1sbegin if (clr) begin counter = 0; enable = 0; end else begin counter = counter +1; if (counter = 25'd249) / 仿真时可将闸门信号设

9、为0.00001s，加快仿真速度/ if (counter = 25'd24999999) / 执行设计时将闸门信号改回为1s begin enable = enable; counter = 25'd0; end endendalways (posedge clk) /?begin if (clr) begin en1 <= 1'b0; en2 <= 1'b0; end else begin en1 <= enable; en2 <= en1; end endassign second_en = (!en1) && (e

10、n2);always (posedge clk) begin if(clr) begin amin1<=0; amin0<=0; ahour1<=0; ahour0<=0; smin1<=0; smin0<=0; shour1<=0; shour0<=0; mmin1<=0; mmin0<=0; mhour1<=0; mhour0<=0; count<=0; end else if (second_en) begin count<=count+1; / if(mode=2'b01) /闹铃调时状态 if

11、(turn=1) /当turn为高电平时调整分位 if(amin1=5)&&(amin0=9) begin amin1<=0; amin0<=0; end else if(amin0=9) begin amin1<=amin1+1; amin0<=0; end else amin0<= amin0+1; else /当turn为低电平时调整小时位 if(ahour1=2)&&(ahour0=3) begin ahour1<=0; ahour0<=0; end else if(ahour0=9) begin ahour1&

12、lt;=ahour1+1; ahour0<=0; end else ahour0<=ahour0+1; / if(mode=2'b10) /时钟调时状态 if(turn=1) /当turn为高电平时调整分位 if(smin1=5)&&(smin0=9) begin smin1<=0; smin0<=0; end else if(smin0=9) begin smin1<=smin1+1; smin0<=0; end else smin0<=smin0+1; else /当turn为低电平时调整小时位 if(shour1=2)&a

13、mp;&(shour0=3) begin shour1<=0; shour0<=0; end else if(shour0=9) begin shour1<=shour1+1; shour0<=0; end else shour0<=shour0+1; else /以下是常规显示begin if(count=59) begin count<=0; smin0<=smin0+1; if (smin0=9) begin smin0<=0; smin1<=smin1+1; if (smin1=5) begin smin1<=0;sh

14、our0<=shour0+1;if (shour0=3)begin shour0<=0; shour1<=shour1+1; if (shour1=2) shour1<=0;end endendendend / if(mode=2'b11) begin /秒表计时状态 if(pause=0) /当pause为低电平时开始计时 begin mmin0<=mmin0+1; if(mmin0=9) begin mmin0<=0; mmin1<=mmin1+1; if(mmin1=9) begin mmin1<=0; mhour0<=mho

15、ur0+1; if (mhour0=9) begin mhour0<=0;mhour1<=mhour1+1;if (mhour1=9) mhour1<=0; end endend endend end end assign LD_alert=(amin1|amin0|ahour1|ahour0)?1:0; /当闹铃有定时后LD_alert发光以示闹铃已定assign sec=enable; /将秒针接到LED灯always(posedge clk) begin if(clr) alert<=0; else if(amin1=smin1)&&(amin0=

16、smin0)&&(ahour1=shour1)&&(ahour0=shour0) alert<=1; /对闹铃做检查，时间到时发光 else alert<=0; end/以下为选择显示模块always (posedge clk)begin if(clr) begin min1<=0; min0<=0; hour1<=0; hour0<=0; endelse begin case(mode) 2'b01: begin /mode=01时，显示闹铃模块 min1<=amin1; min0<=amin0; hou

17、r1<=ahour1; hour0<=ahour0; end 2'b10: begin /mode=10时，显示校时模块 min1<=smin1; min0<=smin0; hour1<=shour1; hour0<=shour0; end 2'b11: begin /mode=11时，显示秒表模块 min1<=mmin1; min0<=mmin0; hour1<=mhour1; hour0<=mhour0; end 2'b00: begin /其他状态，显示普通时钟模块 min1<=smin1; min

18、0<=smin0; hour1<=shour1; hour0<=shour0; end endcase end end endmodule译码模块module display(q,ctr,h1,h0,m1,m0,clk,reset);output6:0q;output3:0 ctr;input3:0 h1,h0,m1,m0;input clk,reset;reg6:0 q;reg25:0 count;reg3:0 temp;reg3:0 scan;/delay yanshi(clk,clk2);always (posedge clk) begin if (reset) beg

19、in count = 0; end else begin count = count +1; endendalways (posedge clk ) /Seg Scan begin if(reset)begin scan<=4'b0000;endelse case(count1:0) / 仿真时将扫描信号频率加快1000倍/ case(count11:10) / 执行设计时将扫描频率改回 2'b00: scan<=4'b0111; 2'b01: scan<=4'b1011; 2'b10: scan<=4'b1101

20、; 2'b11: scan<=4'b1110; endcaseendassign ctr = scan;always (posedge clk) /Seg Scanbegin if(reset)begin temp<=4'b0000;endelse case(count1:0) / 仿真时将扫描信号频率加快1000倍/ case(count11:10) / 执行设计时将扫描频率改回 2'b00: temp<=h1; 2'b01: temp<=h0; 2'b10: temp<=m1; 2'b11: temp&l

21、t;=m0; endcaseendalways (posedge clk) /数码管译码begin if(reset)begin q<=7'b0000000;endelse case(temp)4'd0:q<=7'b0000001; /04'd1:q<=7'b1001111; /14'd2:q<=7'b0010010; /24'd3:q<=7'b0000110; /34'd4:q<=7'b1001100; /44'd5:q<=7'b0100100;

22、/54'd6:q<=7'b0100000; /64'd7:q<=7'b0001111; /74'd8:q<=7'b0000000; /84'd9:q<=7'b0000100; /9default:q<=7'b0000001; endcaseendendmoduleUCF文件NET "clk" LOC = "B8" # 50M# Pin assignment for DispCtl# Connected to Basys2 onBoard 7q displ

23、ayNET "q<6>" LOC = "L14" # Bank = 1, Signal name = CANET "q<5>" LOC = "H12" # Bank = 1, Signal name = CBNET "q<4>" LOC = "N14" # Bank = 1, Signal name = CCNET "q<3>" LOC = "N11" # Bank = 2, Signal

24、 name = CDNET "q<2>" LOC = "P12" # Bank = 2, Signal name = CENET "q<1>" LOC = "L13" # Bank = 1, Signal name = CFNET "q<0>" LOC = "M12" # Bank = 1, Signal name = CG#NET "dp" LOC = "N13" # Bank = 1, Signa

25、l name = DPNET "ctr<3>" LOC = "K14" # Bank = 1, Signal name = AN3NET "ctr<2>" LOC = "M13" # Bank = 1, Signal name = AN2NET "ctr<1>" LOC = "J12" # Bank = 1, Signal name = AN1NET "ctr<0>" LOC = "F12"

26、; # Bank = 1, Signal name = AN0NET "reset" LOC = "N3" # Bank = 2, Signal name = SW7NET "mode<1>" LOC = "E2" # Bank = 3, Signal name = SW6NET "mode<0>" LOC = "F3" # Bank = 3, Signal name = SW5NET "turn" LOC = "G3&q

27、uot; # Bank = 3, Signal name = SW4NET "pause" LOC = "B4" # Bank = 3, Signal name = SW3NET "LD_alert" LOC = "P7" ; # Bank = 3, Signal name = LD2NET "alert" LOC = "M11" ; # Bank = 2, Signal name = LD1NET "sec" LOC = "M5" ;

28、 # Bank = 2, Signal name = LD0testbenchmodule tb_test;/ Inputsreg clk;reg reset;reg 1:0 mode;reg turn;reg pause;/ Outputswire 6:0 q;wire 3:0 ctr;wire sec;wire alert;wire LD_alert;/ Instantiate the Unit Under Test (UUT)clk uut (.clk(clk), .reset(reset), .mode(mode), .turn(turn), .pause(pause), .q(q),

29、 .ctr(ctr), .sec(sec), .alert(alert), .LD_alert(LD_alert); parameter PERIOD = 10; always begin clk = 1'b0; #(PERIOD/2) clk= 1'b1; #(PERIOD/2); endinitial begin/ Initialize Inputsreset = 1;mode = 2'b00;turn = 0;pause = 0;/ Wait 100 ns for global reset to finish#500;reset = 0;mode = 2'b00;turn = 0;#600000;mode = 2'b01;turn = 0;#60000;mode = 2'b01;turn = 1;#60000;mode = 2'b10;turn = 0;#60000;mode = 2'b10;turn = 1;#60000;mode = 2'b11;#60000;pause