计数显示电路设计

1、课程名称：VHDL数字系统设计与测试题 目 计数显示电路 学 院 电子工程学院 学 号 1202121273 姓 名 马泽伟 一 设计功能和要求要求：设计一个输出为3位BCD码的计数显示电路。该计数显示电路由三个模块构成：1、十进制计数器（BCD_CNT）2、七段显示译码器电路（DEC_LED）3、分时总线切换电路（SCAN）。该电路功能为通过对外部一信号脉冲进行计数，并以十进制进行计数，计到百位。同时利用数码管动态扫描原理进行三位数码管进行显示出来。二 设计思路整个设计分十进制计数器模块（BCD_CNT）、分时总线切换电路模块（SCAN）和七段显示译码器电路模块（DEC_LED）构成。总的输

2、入为十进制计数器时钟clk_1k，异步复位清零信号rst_n，分时总线切换电路时钟clk_1m。在rst信号为0期间，在每个clk的上升沿计数器将加1。在每个clk_1k的上升沿将会改变对三个数码管的扫描选通。总的输出为数码管选通信号sel（三位），输出到七段数码管的数据信号led（七位）。电路原理图如下：根据设计思路，设计详细的电路原理图如下：利用quartus进行综合生成RTL电路如下图：顶层模块逻辑结构图如下：顶层模块主要将十进制计数器、分时总线切换和七段显示译码模块进行连接搭建。其中从十进制模块中输出的data13:0、data23:0、data33:0分别为个、十、百位的BCD码。分

3、时总线切换的输出data3:0为其中要显示的一个BCD码和位选信号一一对应。1.十进制计数模块十进制模块输入输出IO口有计数时钟输入sysclk、系统复位端rst_b、BCD输出端data和进位端co。当计数时钟端来一脉冲时，data将会计数，当来10个脉冲时，data端将会清零，并且产生一个进位脉冲信号。如此将三个十进制模块通过进位端co进行级联，则可成为百位BCD计数器。2.分时总线切换这个模块时本设计的重点和难点，分时总线切换经过系统时钟进行分频得到扫描时钟，每当扫描时钟上升沿时，进行切换，使得当data_sel2:0=”011”,data3:0=data13:0,依次类推。3.七段显示

4、译码将data3:0的BCD码译码成为数码管显示码，采用共阴极.四：源代码设计1.顶层模块代码LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY declariation ENTITY display IS PORT ( Global system input sysclk : in STD_LOGIC; rst_b : in STD_LOGIC; tim_clk: in STD_LOGIC; Output ports data_sel : out STD_LOGIC_VECTOR

5、(2 DOWNTO 0); data_ out : out STD_LOGIC_VECTOR(6 DOWNTO 0) ); END ENTITY; Architecture declaritionARCHITECTURE code of display isSignal declarationSIGNAL data1,data2,data3 : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL temp : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL co1,co2 : STD_LOGIC;COMPONENT BCD_CNTCOMPONENT

6、BCD_CNT PORT ( Sysclk : IN STD_LOGIC; rst_b : IN STD_LOGIC; dataout: OUT STD_LOGIC_VECTOR (3 DOWNTO 0); co : OUT STD_LOGIC ); END COMPONENT;COMPONENT DEC_LEDCOMPONENT DEC_LED PORT ( data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data_out : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END COMPONENT;COMPONENT SCAN

7、COMPONENT SCAN PORT ( sysclk : IN STD_LOGIC; rst_b : IN STD_LOGIC; data1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); data_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END COMPONENT; BEG

8、IN U1: BCD_CNT PORT MAP (sysclk => tim_clk,rst_b => rst_b,dataout => data1,co => co1); U2: BCD_CNT PORT MAP (sysclk => co1 , rst_b => rst_b,dataout => data2,co => co2); U3: BCD_CNT PORT MAP (sysclk => co2 ，rst_b => rst_b,dataout => data3); U4: SCAN PORT MAP (sysclk =

9、> sysclk , rst_b => rst_b,data1 => data1, data2=>data2, data3 => data3, data_out => temp, data_sel => data_sel); U5: DEC_LED PORT MAP (data_in => temp, data_out => data_out); END code;1. 十进制模块该模块完成bcd码的计数过程，每当系统时钟的上升沿到来，计数器的低位加1，满10进位，依次类推完成计数功能，复位信号使计数器清零。源程序如下：LIBRARY IE

10、EE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;Entity declarationENTITY BCD_CNT IS PORT ( sysclk : IN STD_LOGIC; rst_b : IN STD_LOGIC; dataout: OUT STD_LOGIC_VECTOR (3 DOWNTO 0); co : OUT STD_LOGIC );END BCD_CNT;Architecture declarationARCHITECTURE cnt OF BCD_CNT ISSignal declartio

11、nSIGNAL temp : STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN PROCESS (sysclk,rst_b) BEGIN IF rst_b = '0' THEN temp <= "0000" ELSIF sysclk'event AND sysclk = '1' THEN IF temp = "1001" THEN temp <= "0000" ELSE temp <= temp + '1' END IF; END IF;

12、 END PROCESS; PROCESS(temp) BEGIN IF temp = "0000" THEN co <= '1' ELSE co <= '0' END IF; END PROCESS; dataout <= temp;END cnt；2.分时总线切换模块也即数码管刷新电路，其实质是一个在高频时钟控制下的多路数据选择器，在这里为三路数据选择器。源程序如下：LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; En

13、tity declarationENTITY SCAN IS PORT ( Global input ports sysclk : IN STD_LOGIC; rst_b : IN STD_LOGIC; data1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Output ports data_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); data_sel : OUT ST

14、D_LOGIC_VECTOR(2 DOWNTO 0) ); END ENTITY; Architecture declarationARCHITECTURE code OF SCAN ISSignal declarationSIGNAL count : STD_LOGIC_VECTOR (3 DOWNTO 0);SIGNAL SEL_NUM : STD_LOGIC_VECTOR (1 DOWNTO 0);BEGIN PROCESS(sysclk,rst_b) BEGIN IF rst_b = '0' THEN count <= "0000" ; ELS

15、IF sysclk'event AND sysclk = '1' THEN count <= count + '1' END IF; END PROCESS; PROCESS (count,sysclk,rst_b) BEGIN IF rst_b = '0' OR SEL_NUM = "11" THEN SEL_NUM <= "00" ELSIF sysclk'event AND sysclk = '1' THEN IF count = "0000&qu

16、ot; THEN SEL_NUM <= SEL_NUM + '1' END IF; END IF; END PROCESS; PROCESS (SEL_NUM) BEGIN CASE SEL_NUM IS WHEN "00" => data_sel <= "011" WHEN "01" => data_sel <= "101" WHEN "10" => data_sel <= "110" WHEN OTHERS =&g

17、t; data_sel <= "111" END CASE; END PROCESS; PROCESS (SEL_NUM) BEGIN CASE SEL_NUM IS WHEN "00" => data_out <= DATA1; WHEN "01" => data_out <= DATA2; WHEN "10" => data_out <= DATA3; WHEN OTHERS => data_out <= "0000" END CASE;

18、 END PROCESS; END code; 3.七段显示译码电路模块根据七段数码管的显示原理，将bcd码译成为数码管所能显示的字符。源程序如下：LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;Entity declaritionENTITY DEC_LED IS PORT ( data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data_out : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END ENTITY;Architecture declaritionArchitecture cod

19、e OF DEC_LED IS BEGIN PROCESS(data_in) BEGIN CASE data_in IS WHEN "0000" => data_out <= "1000000" WHEN "0001" => data_out <= "1111001" WHEN "0010" => data_out <= "0100100" WHEN "0011" => data_out <= "0

20、110000" WHEN "0100" => data_out <= "0011001" WHEN "0101" => data_out <= "0010010" WHEN "0110" => data_out <= "0000010" WHEN "0111" => data_out <= "1111000" WHEN "1000" => data_out <= "0000000" WHEN "1001" => data_out <= "0010000" WHEN OTHERS => data_out <= "1111111&