EDA实验五 状态机VIP

1、 实验五有限状态机0900210204 吴韦艳 一、实验目的：本次实验通过Verilog硬件语言编写摩尔型有限状态机和米勒型有限状态机，掌握采用有限状态机产生各种控制信号的原理，熟悉如何选用合适的有限状态机进行电路设计，通过实验进一步了解原理图编辑方法和仿真方法。二、实验要求： 1、利用Verilog硬件语言，参考提供的源程序，设计一个采用摩尔型有限状态机实现的流水灯控制程序； 2、利用Verilog硬件语言，参考提供的源程序，设计一个采用米勒型有限状态机实现的串行口发送程序； 3、利用Verilog硬件语言，参考提供的源程序，设计一个采用米勒型有限状态机实现的串行口接收程序； 4、利用原理图

2、编辑方法，将串行口发送和接收模块进行连接，实现完整的串行通信电路， 并对该电路进行仿真。三、实验内容1、米勒型有限状态机实现的串行口发送源程序 module s_tx(clk,en,dain,txd); input clk,en; input7:0 dain; output txd; reg 7:0 da_temp; reg txd; reg 3:0 state; parameter swait=4'b0000, star=4'b0001, s1=4'b0010, s2=4'b0011, s3=4'b0100, s4=4'b0101, s5=4&

3、#39;b0110, s6=4'b0111, s7=4'b1000, s8=4'b1001, stop=4'b1010; always (posedge en) da_temp<=dain; always (posedge clk) if (!en) begin state<=swait; txd<=1; end else case(state) swait: begin state<=star;txd<=1; end star: begin state<=s1; txd<=0; end /状态转换s1: begin s

4、tate<=s2; txd<=da_temp7; end s2: begin state<=s3; txd<=da_temp6; end s3: begin state<=s4; txd<=da_temp5; end s4: begin state<=s5; txd<=da_temp4; end s5: begin state<=s6; txd<=da_temp3; end s6: begin state<=s7; txd<=da_temp2; end s7: begin state<=s8; txd<=da_

5、temp1; end s8: begin state<=stop; txd<=da_temp0; end stop: begin state<=stop; txd<=1; end endcase endmodule 2、米勒型有限状态机实现的串行口接收源程序 module s_rx(clk,dain,daout);input clk,dain;output 7:0 daout;reg 7:0 daout;reg 7:0 da_temp;reg 3:0 state;parameter star=4'b0000,s1=4'b0010,s2=4'b00

6、11,s3=4'b0100,s4=4'b0101,s5=4'b0110,s6=4'b0111,s7=4'b1000,s8=4'b1001,stop=4'b1010;always (negedge clk)case (state)star: if (dain)state<=star;elsestate<=s1; /数据开始位为0s1:begin state<=s2; da_temp7<=dain; end /状态转换s2:begin state<=s3; da_temp6<=dain; ends3:beg

7、in state<=s4; da_temp5<=dain; ends4:begin state<=s5; da_temp4<=dain; ends5:begin state<=s6; da_temp3<=dain; ends6:begin state<=s7; da_temp2<=dain; ends7:begin state<=s8; da_temp1<=dain; end /8个状态s8:begin state<=stop; da_temp0<=dain; end /数据结束位为1stop:if (!dain)state<=stop;elsebeginstate<=star;daout<=da_temp;endendcaseEndmodule3