集成电路封装介绍（精品ＰＰＴ）

1、w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o m集成电路封装 港湾网络通用IC组w w w . h a r b o u r n e t w o r k s . c o m 封装功能n封装的定义：内含一个或多个半导体芯片的一种外壳，可提供电连接及机械和环境保护n封装的发展趋势：更多的引脚数，更大的热耗散，更高的封装密度和多芯片封装，以便改进电子系统的性能，使其具有更多的功能及更强的能力。w w w . h a r b o u r n e t w o r k s .

2、c o m 与封装相关的常用参数nATAB TAB焊球阵列 TAB ball grid arraynBGA 焊球阵列 Ball grid arraynCC 片式载体 Chip carriernC4 受控塌陷芯片连接 nCERDIP 玻璃熔封陶瓷双列直插封装 nCMOS 互补金属氧化物半导体nCQFP 陶瓷四边引线扁平封装nDIP 双列直插封装 Dual in-line packagenECL 射级耦合逻辑nFQFP 窄节距四边引线扁平封装 Fine pitch quad flat packnLCC 无引线片式载体 Leadless chip carrierw w w . h a r b o u

3、 r n e t w o r k s . c o mnLCC 无引线片式载体 Leadless chip carriernLGA 面或无引线焊点阵列 Leadless(land) grid arraynLSI 大规模集成 nMCM 多芯片模块 Multichip modulenMCP 多芯片封装nMSI 中规模集成nPBGA 塑球焊球阵列 Plastic ball grid arraynPGA 针栅阵列 Pin grid arraynPLCC 塑料有引线片式载体 Plastic leaded chip carriernPWB 印制线路板 nQFP 四边引线扁平封装 Quad flat pack

4、nQUIP 四边直插封装 Quad in-line packagenSIMM 单边直插存储器模块 Singe in-line memory modulenSIP 单列直插 Single in-line packagenSMTPGA 表面安装针栅阵列 Surface mount pin grid arrayw w w . h a r b o u r n e t w o r k s . c o mnSO 小外形 Small outlinenSOJ J形引线的SOP Small outline J leadnSOP 小外形封装 Sop outline packagenSOT 小外形晶体管 nSSOP

5、 缩小的小外形封装 Shrink small outline packagenSOIC 小外形IC Small outline ICnTAB 载带自动焊 Metric TABnTCE 热膨胀系数nTCM 导热模块nTQFP 薄形四边引线扁平封装 Thin quad flat packnTSOP 薄形小外形封装 Thin small outline packagenTSSOP 薄形缩小的小外形封装 Thin shrink small outline packagenVLSI 超大规模集成nZIF 零插入力nZIP 单边交叉双列直插封装 Zig-zag in-line packagew w w .

6、 h a r b o u r n e t w o r k s . c o m 集成电路发展历程封装类型缩写词60年代70年代80年代90年代双列直插封装DIPYYYY扁平封装FPYYY片式载体CC无引线片式载体LCCYYYY塑料有引线片式载体PLCCYYY栅阵列针栅阵列PGAYYYYw w w . h a r b o u r n e t w o r k s . c o m封装类型缩写词60年代70年代80年代90年代无引线（面）栅阵列LGAYY小外形或小外形ICSO或SOICYYY小外形J形引线SOJYY载带自动焊TABYYY列直插封装单列直插封装SIPYYYY单边交叉双列直插封装ZIPYYY

7、四边单列直插封装QUIPYYY单列直插存储器模块SIMM（SIP）YYw w w . h a r b o u r n e t w o r k s . c o m封装类型缩写词60年代70年代80年代90年代四边引线扁平封装QFPYYY模塑形载体MRCYY窄节距四边引线扁平封装FQFPY薄形四边引线扁平封装TQFPY窄节距小外形封装SSOPY薄形缩小的小外形封装TSSOPY栅阵列Y焊球阵列BGAYw w w . h a r b o u r n e t w o r k s . c o m封装类型缩写词60年代70年代80年代90年代塑料焊球阵列PBGAY载带自动焊球阵列ATABY表面安装型针栅阵列

8、SMTPGAY公制的TABTABYY多芯片模块MCMYYYYMCM针栅阵列MCMPGAYYY缩小的DIPYY多I/O引脚数SIMMSIMM（SIP）Yw w w . h a r b o u r n e t w o r k s . c o mn微电子封装一般可分为微电子封装一般可分为 4级级 ,如图如图 所示所示 ,即即 :n0级封装级封装芯片上器件本体的互连芯片上器件本体的互连n1级封装级封装芯片芯片 (1个或多个个或多个 )上的输入上的输入 /输出与基板互连输出与基板互连 n2级封装级封装将封装好的元器件或多芯片将封装好的元器件或多芯片组件用多层互连布线板组件用多层互连布线板 ()组装成电组

9、装成电子部件子部件 ,插件或小整机插件或小整机n3级封装级封装用插件或小整机组装成机柜用插件或小整机组装成机柜整机系统整机系统w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o m半导体制造装备概述n芯片制造（前道）芯片制造（前道） 单晶硅拉制、切片、表面处理、光刻、减薄、单晶硅拉制、切片、表面处理、光刻、减薄、划片划片n 芯片封装（后道）芯片封装（后道） 测试、测试、 滴胶、滴胶、Die bonding、Wire bonding、压模压模w w w . h a r b

10、 o u r n e t w o r k s . c o mn 半导体封装的基本形式半导体封装的基本形式n双列直插式封装双列直插式封装 ()n表面安装技术表面安装技术 () 无引线陶瓷片式载体无引线陶瓷片式载体() 塑料有引线片式载体塑料有引线片式载体 () 四边引线扁平封装四边引线扁平封装 () 四边引线塑料扁平封装四边引线塑料扁平封装 ()n平面阵列型平面阵列型 (）n球栅阵列封装球栅阵列封装 ()w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w .

11、 h a r b o u r n e t w o r k s . c o mChip to substrate interconnect technologiesw w w . h a r b o u r n e t w o r k s . c o m将带引线的芯片从载带上切下的示意图外引线键合过程示意图w w w . h a r b o u r n e t w o r k s . c o m技术中的载带w w w . h a r b o u r n e t w o r k s . c o mn概括而言 ,电子封装技术已经历了四代 ,现正在进入第五代。n第一代 ： 60年代前采用的是接线板焊接

12、的方式 ,框架为电路板 ,主要插装元件是电子管。n第二代 ：60年代采用穿孔式印刷电路板()封装 ,主要元件是晶体管和柱型元件。n第三代 ：70年代用自动插装方式将为代表的集成电路封装在板上 ,这是穿孔式封装技术的全盛时期。n第四代 ：从 80年代开始 ,采用将表面安装元件 ()和表面安装器件 ()安装在表面上。这一封装技术的革命改变了元器件和电子产品的面貌。n第五代 ：这是 90年代显露头角的微封装技术 ,是上一代封装技术的发展和延伸 ,是将多层技术、高密度互连技术、微型元器件封装技术综合并发展 ,其代表性技术就是金属陶瓷封装 (),典型产品是M。最近由于系统级芯片 ()和全片规模集成 ()

13、技术的发展 ,微电子封装技术正孕育着重大的突破w w w . h a r b o u r n e t w o r k s . c o mn向表面安装技术向表面安装技术 ()发展发展n1988年技术约占封装市场份额的年技术约占封装市场份额的17.5% , 1 993年占年占 44% , 1 998年占年占 75%。传统的双列直插。传统的双列直插封装所占份额越来越小封装所占份额越来越小 ,取而代之的是表面安装取而代之的是表面安装类型的封装类型的封装 ,如有引线塑料片式载体如有引线塑料片式载体 ,无引线陶瓷无引线陶瓷片式载体片式载体 ,四边引线塑料扁平封装四边引线塑料扁平封装 ,塑料球栅阵列塑料球栅

14、阵列封装封装 ()和陶瓷球栅阵列封装和陶瓷球栅阵列封装 ()等等 ,尤其是和两种类型最具典型尤其是和两种类型最具典型.w w w . h a r b o u r n e t w o r k s . c o mn向高密度发展向高密度发展n目前目前 ,陶瓷外壳陶瓷外壳 ()已达已达 1089只管只管脚、达脚、达 625只管脚、间距达只管脚、间距达 0.5、达、达 376只管脚、达只管脚、达 1 0 0 0只管脚。只管脚。n根据美国发展规划根据美国发展规划 ,到到 2 0 0 7年年 ,最最大芯片尺寸将增大到大芯片尺寸将增大到 1 0 0 0*2 ,同时每同时每枚芯片上的输入枚芯片上的输入 /输出数

15、最多将达到输出数最多将达到 50 0 0个个 ,焊点尺寸将缩小到焊点尺寸将缩小到 0.127以下以下w w w . h a r b o u r n e t w o r k s . c o m从单芯片封装向多芯片封装发展从单芯片封装向多芯片封装发展起步于起步于 90年代初年代初 ,由于的高密度、高性能由于的高密度、高性能和高可靠性而倍受青睐。受到世界各国的极大关注和高可靠性而倍受青睐。受到世界各国的极大关注 ,纷纷纷投入巨额资金纷投入巨额资金 ,如美国政府如美国政府 3年投入年投入 5亿美元亿美元 ,在在 1 0年投入年投入 1 0亿美元来发展亿美元来发展 ,据预测据预测 , 1 999年全球产

16、品销售额将达年全球产品销售额将达 2 0 0亿美元。目前最高亿美元。目前最高水平的水平的是的产品是的产品 ,2 0 0*2 、78层、层、3 0 0多万个通孔多万个通孔 , 1 40 0互连线互连线 , 1 80 0只管脚只管脚 , 2 0 0功耗功耗w w w . h a r b o u r n e t w o r k s . c o m由陶瓷封装向塑料封装发展由陶瓷封装向塑料封装发展在陶瓷封装向高密度在陶瓷封装向高密度 ,多引线和低功耗展的同时多引线和低功耗展的同时 ,越来越多的领域正在由塑料封装所取代。而且越来越多的领域正在由塑料封装所取代。而且 ,新的塑料封装形式层出不穷新的塑料封装形

17、式层出不穷 ,目前以和目前以和为主为主 ,全部用于表面安装全部用于表面安装 ,这些塑料封装这些塑料封装占领着占领着 90 %以上的市场以上的市场w w w . h a r b o u r n e t w o r k s . c o m高密度封装中的关键技术高密度封装中的关键技术从技术发展观点来看从技术发展观点来看 ,作为高密度封装的关键技术主要作为高密度封装的关键技术主要有有 : , , , ,和三维封装和三维封装载带封装载带封装它可以提供超窄的引线间距和很薄的封装外形它可以提供超窄的引线间距和很薄的封装外形 ,且在板上占据很小的面积且在板上占据很小的面积 ,可用于高可用于高/数的数的和微处理

18、器和微处理器 ,东芝公司东芝公司1 996年问世的笔记年问世的笔记本电脑中就使用了承载本电脑中就使用了承载 ,其引线间距其引线间距 0.2 5 ,焊接精度为焊接精度为 3 0 ,据报道据报道 ,最小间距最小间距可达可达 0.1 5w w w . h a r b o u r n e t w o r k s . c o m球栅阵列封装球栅阵列封装(BGA)技术的最大特点是器件与板之间的互连由引线改为小球 ,制作小球的材料通常采用合金焊料或有机导电树脂。采用技术容易获得/数超过 60 0个的封装体。由于完全采用与相同的回流焊工艺 ,避免了中的超窄间距 ,可以提供较大的焊盘区 ,因此使焊接工艺更加简单

19、 ,强度大大提高 ,可靠性明显改善w w w . h a r b o u r n e t w o r k s . c o m的尺寸通常大于(芯片规模封装 ),在 2 1 40之间。可分为塑料()、陶瓷()或载带()。在中 ,通常用引线键合采用焊球或引线键合将芯片贴在陶瓷基板上 ;在中 ,用标准内引线键合工艺或焊球将芯片贴在其带状框架上w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c

20、o m 芯片规模封装与芯片尺寸封装芯片规模封装与芯片尺寸封装 ()芯片规模封装与芯片尺寸封装统称为芯片规模封装与芯片尺寸封装统称为 ,它被认为是它被认为是本世纪先进封装的主流技术。在芯片规模封装中本世纪先进封装的主流技术。在芯片规模封装中 ,封装体封装体的尺寸是芯片尺寸的的尺寸是芯片尺寸的 1.2倍以下倍以下 ;芯片尺寸封装中封装芯片尺寸封装中封装体的尺寸与芯片尺寸基本相当。这是在电路板面积不变的体的尺寸与芯片尺寸基本相当。这是在电路板面积不变的前提下前提下 ,希望更换大芯片的集成电路时提出的。在这种情希望更换大芯片的集成电路时提出的。在这种情况下况下 ,将框架引线伸展到芯片上方形成芯片引线将

21、框架引线伸展到芯片上方形成芯片引线 (),封装尺寸不变封装尺寸不变 ,芯片面积增大芯片面积增大 ,封装体面积与芯片面积的比封装体面积与芯片面积的比值变小值变小w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o m多芯片组件多芯片组件 ( )将多只合格的裸芯片将多只合格的裸芯片 ()直接封装在多层互连基板直接封装在多层互连基板上上 ,并与其它元器件一起构成具有部件或系统功能的多芯并与其它元器件一起构成具有部件或系统功能的多芯片组件片组件 (),已成为蜚声全球的已成为蜚声全

22、球的 90年代代表性技术。年代代表性技术。w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mMCM封装封装w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mDie Bondingw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k

23、s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mHistory and applications of wirebondingWirebonding is the earliest technique of device assembly, whose first result was published by Bell Laboratories in 1957. Sine then, the technique has been extreme

24、ly developedw w w . h a r b o u r n e t w o r k s . c o m AdvantagenFully automatic machines have been developed for volume production.nBonding parameters can be precisely controlled; mechanical properties of wires can be highly reproduced.nBonding speed can reach 100-125 ms per each wire interconne

25、ction (two welds and a wire loop).nMost reliability problems can be eliminated with properly controlled and much improved tools (capillaries and wedges) and processes.nSpecific bonding tools and wires can be selected by packaging engineers to meet the requirements.nInfrastructure of the technique ha

26、s been comprised by large wirebonding knowledge, manufacturing people, equipment venders and materials.w w w . h a r b o u r n e t w o r k s . c o mThe most popular applications that use wirebonding are: Single and multitiered cofired ceramic and plastic ball grid arrays (BGAs), single chip and mult

27、ichip Ceramic and plastic quad flat packages (CerQuads and PQFPs) Chip scale packages (CSPs) Chip on board (COB)Ball bondWedge bondWirebonding的基本形式的基本形式w w w . h a r b o u r n e t w o r k s . c o mFirst and second bond comparison. (A) Ball bonding first bond. (B) Ball bonding second bond: stitch bon

28、d and tail bond. (C) Wedge bonding first bond. (D) Wedge bonding second bond.w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o m Wedge bondthe bonding process can be defined to three major processes: thermocompression bonding (T/C) ultrasonic bonding (U/S)therm

29、osonic bonding (T/S)as shown in Table 1-1w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mBall Bondingw w w . h a r b o u r n e t w o r k s . c o mThe capillaries are typically 1.585 mm in diameter and 11.1 mm long

30、.They have a large entry hole at the top and then the hole tapersdown to a small hole diameter typically between 38-50 mm,w w w . h a r b o u r n e t w o r k s . c o m40-m pad pitch ball andwedge first bond comparison.w w w . h a r b o u r n e t w o r k s . c o mSchematic of different looping. (A)Ba

31、ll bonding looping. (B) Traditional wedge radial bonding looping. (C) Wedge bonding Constant Gap looping.w w w . h a r b o u r n e t w o r k s . c o m40 mm pitch first bond.w w w . h a r b o u r n e t w o r k s . c o m40 mm looping. Short wires are to ground. Long wires are to the leads.w w w . h a

32、r b o u r n e t w o r k s . c o mWedge stitch bonding.w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mLimitation of wirebon

33、dingFor the application of wirebonding method, terminals of chips have to be arranged at the periphery of the chips, otherwise short circuit is easily caused. Therefore, wirebonding technique is difficult for high I/O(500) interconnections.w w w . h a r b o u r n e t w o r k s . c o m Bonding parame

34、tersBonding parameters are extremely important because they control the bonding yield and reliability directly.The key variables for wire bonding include: Bonding force and pressure uniformity Bonding temperature Bonding time Ultrasonic frequency and powerw w w . h a r b o u r n e t w o r k s . c o

35、m Bond designBall bonding Ball size is approximately 2 to 3 times the wire diameter, 1.5 times for small ball applications with fine pitches, and 3 to 4 times for large bond pad application. Bond size should not exceed 3/4 of the pad size, about 2.5 to 5 times the wire diameter, depending on the geo

36、metry and moving direction of capillary during bonding. Loop heights of 150 um are now common, but very depending on the wire diameter and applications. Loop length should be less than 100 times the wire diameter. However, in some cases, high I/Os for instance, wire lengths have to increase to more

37、than 5 mm. The wirebonder must suspend the length of wire between the die and lead frame without vertical sagging or horizontal swaying.w w w . h a r b o u r n e t w o r k s . c o mWedge bonding A high-strength wedge bond is possible even the bond is only 2-3 mm wider than wire diameter. Pad length

38、must support the long dimension of the wedge bond as well as the tail. The pads long axis should be oriented along the intended wire path. Bond pitch must be designed to maintain consistent distance between wires.w w w . h a r b o u r n e t w o r k s . c o m CleaningTo ensure bondability and reliabi

39、lity of wirebond, one of the critical conditions is that the bonding surface must be free of any contaminants. Therefore cleaning is an important work before bonding. The method usually adapted is molecular cleaning method, plasma or UV-ozone cleaning method.w w w . h a r b o u r n e t w o r k s . c

40、 o m Bond evaluationnDestructive bond pull test (Method 2011)nInternal visual (Method 2010; Test condition A and B)nDelay measurements (Method 3003)nNondestructive bond pull test (Method 2023)nBall bond shear testnConstant acceleration (Method 2001; Test condition E)nRandom vibration (Method 2026)nM

41、echanical shock (Method 2002)nStabilization bake (Method 1008)nMoisture resistance (Method 1004)w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mIf both thebonds are at the same level and the hook is appliedat the center, the forces can be representedWhen the

42、 both angles are 30o, the pull force is equal to the breakload. The failure during pull test may occur at one of the five positions in the wirebond structure:A. Lift off first bondB. Wire break at transition first bondC. Wire break mid spanD. Wire break at transition second bondE. Lift off second bo

43、ndWhen properly pulled, the bond should fail at B or D. If failures occur at A, C, or E, then the bonding parameters, metallization, bonding machine, bonding tool, hook, has to be reviewed.w w w . h a r b o u r n e t w o r k s . c o mFlip-Chip Technologyw w w . h a r b o u r n e t w o r k s . c o m

44、Advantages: Smaller size: Smaller IC footprint (only about 5% of that of packaged IC e.g. quad flat pack), reduced height and weight. Increased functionality: The use of flip chips allow an increase in the number of I/O. I/O is not limited to the perimeter of the chip as in wire bonding. An area arr

45、ay pad layout enables more signal, power and ground connections in less space. A flip chip can easily handle more than 400 pads. Improved performance: Short interconnect delivers low inductance, resistance and capacitance, small electrical delays, good high frequency characteristics, thermal path fr

46、om the back side of the die. Improved reliability: Epoxy underfill in large chips ensures high reliability. Flip-chips can reduce the number connections per pin from three to one. Improved thermal capabilities: Because flip chips are not encapsulated, the back side of the chip can be used for effici

47、ent cooling. Low cost: Batch bumping process, cost of bumping decreases, cost reductions in the underfill-processw w w . h a r b o u r n e t w o r k s . c o m Disadvantages: Difficult testing of bare dies. Limited availability of bumped chips. Challenge for PCB technology as pitches become very fine

48、 and bump counts are high. For inspection of hidden joints an X-ray equipment is needed. Weak process compatibility with SMT. Handling of bare chips is difficult. High assembly accuracy needed. With present day materials underfilling process with a considerable curing time is needed. Low reliability

49、 for some substrates. Repairing is difficult or impossible.w w w . h a r b o u r n e t w o r k s . c o m 底部填充工艺 (Underfilling Process）温度膨胀系数小于 3 ppm/的硅器件直接同有机物印制线路板 (温度膨胀系数在1 8 50 ppm/ )压接在一起 ,会产生严重的热机应力和疲劳 ,俗称“热机失配底部填充料锁住倒装片和印制板示意图w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n

50、 e t w o r k s . c o mFlip chip joining using adhesives (isotropic, anisotropic, nonconductive)w w w . h a r b o u r n e t w o r k s . c o mFlip chip joining by thermocompression.Flip chip thermosonic joiningw w w . h a r b o u r n e t w o r k s . c o mFlip chip bonding using thermocompressionw w w

51、. h a r b o u r n e t w o r k s . c o mFlip chip process by solder joining die preparing (testing, bumping, dicing) substrate preparing (flux application or solder paste printing) pick, alignment and place reflow soldering cleaning of flux residues (optional) underfill dispensing underfill curing.w

52、w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mFlip chip joining using adhesivesw w w . h a r b o u r n e t w o r k s . c o

53、mw w w . h a r b o u r n e t w o r k s . c o mIntroduction to CSP TechnologyDescription of various types of CSPsw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mBall Grid Array (BGA) Technologyw w w . h a r b o u r n e t w o r k s . c o mIt is an IC package f

54、or active devices intended for surface mount applicationsIt is an area array package, i.e. utilizing whole or part of the device footprint for interconnectionsThe interconnections are made of balls (spheres) of most often a solder alloy or sometimes other metals More specifically, the BGA package us

55、ually fulfils the following additional requirements:The length of the package body (most often square) ranges from 7 to 50 mmLead counts over 1000 possible, but 50 to 500 range most common todayThe pitch, i.e center-to-center distance, of the balls is generally between 1.0 and 1.5 mmw w w . h a r b

56、o u r n e t w o r k s . c o mFigure 2. A 160-lead 0.3 mm (11.8 mil) pitch QFP placed on a grid of 1.5 mm pitch spheres (bottom side of a PBGAS225).w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mFigure 5. A cross-

57、section of a Tape (or TAB) BGA - TBGA.w w w . h a r b o u r n e t w o r k s . c o mA cross-section of a Super BGA - SBGA.w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o

58、mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o m港湾目前物料属性表中常见的港湾目前物料属性表中常见的IC封装封装大类料号大类描述封装类型05/35大类专用IC/接口器件等BGA、EDQUAD TQFP、ESBGA、FF、FG、PBGA、P-DSO、PEB、P-FQFP、PGA、P-HSBGA、PQFP、P-TQFP、QFP06/3911大类逻辑IC/模拟器件SOIC、TSSOP、SO、SOP、SSOP、PLCC、DIP、SOT、QFP、PQFP、LQFP07/3

59、7大类存储器TSOP、BGA、DIP、PLCC、PQFP、QFP、SO、SOJ、SOP、TQFP、TS0P、11/33/31二三极管/电源调整ICSOT、STC、TO、TSSOP、DIPw w w . h a r b o u r n e t w o r k s . c o m 封装选型建议大类料号大类描述建议优选封装列举05/35大类专用IC/接口器件等由于专用IC的唯一性，无法建议优选封装06/3911大类逻辑IC/模拟器件SOIC、TSSOP、PLCC07/37大类存储器TSOP、BGA、PLCC、TS0P、11/33/31二三极管/电源调整ICSOT、D-PAK、TO、TSSOP、DIP

60、w w w . h a r b o u r n e t w o r k s . c o mn 集成电路芯片封装技术简介n自从美国Intel公司1971年设计制造出4位微处a理器芯片以来，在20多年时间内，CPU从Intel4004、80286、80386、80486发展到Pentium和Pentium，数位从4位、8位、16位、32位发展到64位;主频从几兆到今天的400MHz以上，接近GHz;CPU芯片里集成的晶体管数由2000个跃升到500万个以上;半导体制造技术的规模由SSI、MSI、LSI、VLSI达到 ULSI。封装的输入/输出（I/O）引脚从几十根，逐渐增加到几百根，下世纪初可能达