基于FPGA电子时钟系统编程毕业论文报告

1、目录一、系统设计要求 22、 系统设计方案 2三、 综合及时电路的设计 23.1 计时电路的设计 33.2 计数电路CNT60、CNT30计数模块的具体设计 34、 显示控制电路的设计 44.1 显示控制电路 44.2 显示译码电路 45、 调整控制电路TZKZQ的设计 55.1状态切换电路 55.2 加一调整电路55.3 TZKZQ的输入、输出 56、 系统总体电路组装图 67、 主要的VHDL源程序 67.1 显示控制电路DISPLAY.VHDL源程序 67.2 调整控制电路TZKAQ.VHDL源程序 97.3 计数电路CNT60.VHDL源程序 117.4 计时电路CNT30.VHDL源

2、程序 127.5 系统总体组装电路的源程序 148、 系统仿真/硬件验证 198.1 CNT60.VHDL仿真 198.2 CNT30.VHDL仿真 208.3 DISPLAY.VHDL仿真 208.4 TZKZQ.VHDL仿真 208.5 系统硬件验证 209、 设计技巧分析 2110、 系统拓展思路 2111、 系统设计心得体会 2224 / 24文档可自由编辑打印一、系统设计要求设计一个综合性的计时系统，要求能实现年、月、日、时、分、秒以及星期的计数等中和计时功能，同时将计数结果通过七段数码管或1602液晶显示。设计也能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹

3、钟功能，能在设定的时间发出闹铃音，能非常方便地对年、月、日时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 二、系统设计方案根据系统的设计要求，综合设计系统可分为三个主要模块：综合计时电路模块、显示控制电路模块和调整控制电路模块。其综合控制电路模块主要用于完成年、月、日、十、分、秒及星期的计时功能，显示控制模块主要用于完成各计时结果的显示控制和显示译码等相关的功能，调整控制电路主要用于调整及时电路的初始值即校正显示时间。 状态显示扬声器 主 控 制 电 路 扫描显示模块 天计数器 综 合 计 时 电 路 模 块 周计数器 年计数器 月计数器 二十四 进时 计数六十进分计数六十进秒

4、计数时钟源选 择键手动 校正电路系统复位三、 综合及时电路的设计综合计时电路可分为计秒电路、计分电路、计时电路、计星期电路、计日电路、计月电路和计年电路等7个模块电路，这七个模块电路分别设置了预置数、计数和进位等功能，其设计如下描述：3.1 计秒电路/计分电路/计时电路/计星期电路/ 计日电路/计月电路/计年电路设计用秒脉冲作为计秒电路的计数时钟信号，每当计满60就会溢出，同时进位位进位，计分电路加1，同时计秒电路清零并重新计数。将计秒电路的进位信号作为计分电路的计数时钟信号，每当计满60就会溢出，同时进位位进位，计时电路加1，同时计分电路清零并重新计数。将计分电路的进位信号作为计时电路的计数

5、时钟信号，每当计满24或12就会溢出，同时进位位进位，计星期/日电路加1，同时计时电路清零并重新计数。将计日电路的进位信号作为计星期电路的计数时钟信号，每当计满7就会溢出，计星期电路返回加1并重新计数。将计时电路的进位脉冲信号作为计日电路的计数时钟信号，通过系统辨认，确定本月总天数后，每当计满本月天数就会溢出进位，计月电路加1，计日电路重新计数。将计日电路的进位信号作为计月电路的计数时钟信号，每当计满12就会溢出进位，计年电路加1，计月电路返回加1并重新计数。将计月电路的进位信号作为计年电路的计数时钟信号，每当计满100就会溢出，计年电路返回加1并重新计数。3.2 计数电路CNT60、CNT3

6、0计数模块的具体设计CNT60计数模块是一个多用计时模块，它既可以作为计秒电路调用，又可以作为计分电路调用，如图1是其输入、输出端口图，其中，输入信号LD为置数控制信号，低电平有效，输入信号CLK是计数时钟信号，输入型号DATA为预置数，输出信号NUM为计数结果，输出信号CO为计数溢出信号。 图1. CNT60计数模块输入、输出端口图CNT30计数模块是一个计日模块。由于该计数模块涉及到大小月及闰年问题，所以CNT30的计数范围并不是固定不变，存在28、29、30和31四种计数情况。图2是其输入、输出端口图，其中，输入信号LD为置数控制信号，低电平有效，输入信号CLK是计数时钟信号，输入型号D

7、ATA为预置数，输入YEAR为当前计时的年份数，输入信号MONTH为当前计时的月份数，输出信号NUM为计数结果，输出信号CO为计数溢出信号输出信号CURRUT_MAX_DAYS为当前月的天数。图2 CNT30计数模块输入、输出端口图四、显示控制电路的设计显示主要用数码管显示，主要用于显示当前年、月、日、时、分、秒、及星期，本系统的数据显示电路可分为两个子模块即显示控制电路和显示译码电路。4.1 显示控制电路主要负责完成数据选择扫描及数码管选择信号的产生。数据扫描选择输出，同时对选择的数据进行BCD码转换等功能4.2 显示译码电路将用于显示的BCD码数据进行译码。XSKZQ的输入、输出端口如图3

8、所示。其中，输入信号LD为置数控制信号，低电平有效，输入信号CLK_SCAN是计数时钟信号，输入信号SEC、MIN、HOUR、DAY、MON、YEAR、WEEK分别来自计秒电路、计分电路、计时电路、计日电路、计月电路、计年电路和计星期电路等计时电路的计数结果的输出：输出信号BCD为被选择进行显示的计时电路的计时结果的8为BCD码，输出端 SELOUT经外部的3-8译码电路译码后用于选择对应计时结果显示数码管的公共端五、调整控制电路TZKZQ的设计调整控制电路TZKZQ主要有状态切换模块和加一调整模块，状态切换模块主要负责切换正常时间计数模式和时间调整模式并负责切换调整那个时间块的状态，加一调整

9、模块主要用于对年、月、日、时、分、秒及星期的加一调整，调整调正常的时间是运作。5.1状态切换电路在状态的切换过程中，被选着的状态所对应的二极管点亮，没被选着的状态调整所对应的发光二极管就熄灭，以便调试，被选中的状态就可以用加一按键进行相应的时间调整，知道调整的正确的时间5.2 加一调整电路主要对年、月、日、时、分、秒及星期的加一调整，是本设计很重要的部分，以防止电或出现异常情况出现时间错乱，这时就要对相应的时间模块进行调整，直到对应真确的当地时间。5.3 TZKZQ的输入、输出图4是其输入、输出端口图，其中输入信号KEY1.0为键盘信号，当KEY=10时表示按下了设置键，系统切换到下一状态，当

10、KEY=10时表示按下了调整键，系统进行自加一。输入信号CLK_KEY为按键扫描时钟信号，输入信号YEAR_CUR、MON_CUR、 DAY_CUR、 HOUR_CUR、 MIN_CUR、 SEC_CUR、 WEEK_CUR、 CURRENT_MAX_CUR为各计时电路输出的当前计时结果的反馈值，输出信号YEAR_EN、MON_EN、 DAY_EN、 HOUR_CEN、 MIN_EN、 SEC_EN、 WEEK_EN为各计时电路的异步置数使能信号；输出信号SEC 、MIN 、HOUR、 DAY 、MON 、YEAR、 WEEK为调整后对应时间预置的数。 图4 TZKZQ输入、输出端口图六、系统

11、总体电路图的设计经过系统的分析，系统的电路图由调节控制电路、显示控制电路和和综合计时电路组转而成。由于排版原因，本综合计时系统的组装电路原理图在（下一页）七、主要VHDL源程序7.1 显示控制电路DISPLAY的VHDL源程序-DISPLAY_CONTRAL.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY DISPLAY IS PORT(CLK_SCAN:IN STD_LOGIC; SEC,MIN:IN STD_LOGI

12、C_VECTOR(5 DOWNTO 0); HOUR:IN STD_LOGIC_VECTOR(4 DOWNTO 0); DAY:IN STD_LOGIC_VECTOR(4 DOWNTO 0); MON:IN STD_LOGIC_VECTOR(3 DOWNTO 0); YEAR:IN STD_LOGIC_VECTOR(6 DOWNTO 0); WEEK:IN STD_LOGIC_VECTOR(2 DOWNTO 0); SELOUT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); BCD_DATA:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENT

13、ITY DISPLAY;ARCHITECTURE ART3 OF DISPLAY IS SIGNAL TEMP:INTEGER RANGE 0 TO 99; SIGNAL CNT:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN PROCESS(CLK_SCAN)IS BEGIN IF CLK_SCAN'EVENT AND CLK_SCAN='1'THEN IF CNT<="111"THEN CNT<="000" ELSE CNT<=CNT+'1' END IF; END I

14、F; END PROCESS; SELOUT<=CNT; PROCESS(CNT)IS BEGIN CASE CNT IS WHEN"000"=>TEMP<=CONV_INTEGER(SEC); WHEN"001"=>TEMP<=CONV_INTEGER(MIN); WHEN"010"=>TEMP<=CONV_INTEGER(HOUR); WHEN"011"=>TEMP<=CONV_INTEGER(DAY); WHEN"100"=>TE

15、MP<=CONV_INTEGER(MON); WHEN"101"=>TEMP<=CONV_INTEGER(YEAR); WHEN"110"=>TEMP<=2; WHEN"111"=>TEMP<=CONV_INTEGER(WEEK); WHEN OTHERS=>NULL; END CASE;CASE TEMP IS WHEN 0=>BCD_DATA<="00000000" WHEN 1=>BCD_DATA<="00000001"

16、; WHEN 2=>BCD_DATA<="00000010" WHEN 3=>BCD_DATA<="00000011" WHEN 4=>BCD_DATA<="00000100" WHEN 5=>BCD_DATA<="00000101" WHEN 6=>BCD_DATA<="00000110" WHEN 7=>BCD_DATA<="00000111" WHEN 8=>BCD_DATA<=&quo

17、t;00001000" WHEN 9=>BCD_DATA<="00001001" WHEN 10=>BCD_DATA<="00010000" WHEN 11=>BCD_DATA<="00010001" WHEN 12=>BCD_DATA<="00010010" WHEN 13=>BCD_DATA<="00010011" WHEN 14=>BCD_DATA<="00010100" WHEN 15=

18、>BCD_DATA<="00010101" WHEN 16=>BCD_DATA<="00010110" WHEN 17=>BCD_DATA<="00010111" WHEN 18=>BCD_DATA<="00011000" WHEN 19=>BCD_DATA<="00011001" WHEN 20=>BCD_DATA<="00100000" WHEN 21=>BCD_DATA<="0

19、0100001" WHEN 22=>BCD_DATA<="00100010" WHEN 23=>BCD_DATA<="00100011" WHEN 24=>BCD_DATA<="00100100" WHEN 25=>BCD_DATA<="00100101" WHEN 26=>BCD_DATA<="00100110" WHEN 27=>BCD_DATA<="00100111" WHEN 28=&g

20、t;BCD_DATA<="00101000" WHEN 29=>BCD_DATA<="00101001" WHEN 30=>BCD_DATA<="00110000" WHEN 31=>BCD_DATA<="00110001" WHEN 32=>BCD_DATA<="00110010" WHEN 33=>BCD_DATA<="00110011" WHEN 34=>BCD_DATA<="001

21、10100" WHEN 35=>BCD_DATA<="00110101" WHEN 36=>BCD_DATA<="00110110" WHEN 37=>BCD_DATA<="00110111" WHEN 38=>BCD_DATA<="00111000" WHEN 39=>BCD_DATA<="00111001" WHEN 40=>BCD_DATA<="01000000" WHEN 41=>

22、BCD_DATA<="01000001" WHEN 42=>BCD_DATA<="01000010" WHEN 43=>BCD_DATA<="01000011" WHEN 44=>BCD_DATA<="01000100" WHEN 45=>BCD_DATA<="01000101" WHEN 46=>BCD_DATA<="01000110" WHEN 47=>BCD_DATA<="01000

23、111" WHEN 48=>BCD_DATA<="01001000" WHEN 49=>BCD_DATA<="01001001" WHEN 50=>BCD_DATA<="01010000" WHEN 51=>BCD_DATA<="01010001" WHEN 52=>BCD_DATA<="01010010" WHEN 53=>BCD_DATA<="01010011" WHEN 54=>BC

24、D_DATA<="01010100" WHEN 55=>BCD_DATA<="01010101" WHEN 56=>BCD_DATA<="01010110" WHEN 57=>BCD_DATA<="01010111" WHEN 58=>BCD_DATA<="01011000" WHEN 59=>BCD_DATA<="01011001" WHEN 60=>BCD_DATA<="0110000

25、0" WHEN 61=>BCD_DATA<="01100001" WHEN 62=>BCD_DATA<="01100010" WHEN 63=>BCD_DATA<="01100011" WHEN 64=>BCD_DATA<="01100100" WHEN 65=>BCD_DATA<="01100101" WHEN 66=>BCD_DATA<="01100110" WHEN 67=>BCD_

26、DATA<="01100111" WHEN 68=>BCD_DATA<="01101000" WHEN 69=>BCD_DATA<="01101001" WHEN 70=>BCD_DATA<="01110000" WHEN 71=>BCD_DATA<="01110001" WHEN 72=>BCD_DATA<="01110010" WHEN 73=>BCD_DATA<="01110011&

27、quot; WHEN 74=>BCD_DATA<="01110100" WHEN 75=>BCD_DATA<="01110101" WHEN 76=>BCD_DATA<="01110110" WHEN 77=>BCD_DATA<="01110111" WHEN 78=>BCD_DATA<="01111000" WHEN 79=>BCD_DATA<="01111001" WHEN 80=>BCD_DA

28、TA<="10000000" WHEN 81=>BCD_DATA<="10000001" WHEN 82=>BCD_DATA<="10000010" WHEN 83=>BCD_DATA<="10000011" WHEN 84=>BCD_DATA<="10000100" WHEN 85=>BCD_DATA<="10000101" WHEN 86=>BCD_DATA<="10000110&qu

29、ot; WHEN 87=>BCD_DATA<="10000111" WHEN 88=>BCD_DATA<="10001000" WHEN 89=>BCD_DATA<="10001001" WHEN 90=>BCD_DATA<="10010000" WHEN 91=>BCD_DATA<="10010001" WHEN 92=>BCD_DATA<="10010010" WHEN 93=>BCD_DATA

30、<="10010011" WHEN 94=>BCD_DATA<="10010100" WHEN 95=>BCD_DATA<="10010101" WHEN 96=>BCD_DATA<="10010110" WHEN 97=>BCD_DATA<="10010111" WHEN 98=>BCD_DATA<="10011000" WHEN 99=>BCD_DATA<="10011001"

31、; WHEN OTHERS=>BCD_DATA<="00000000" END CASE; END PROCESS;END ARCHITECTURE ART3;7、2调整控制电路TZKZQ的VHDL源程序-TZKZQ.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY TZKZQ IS PORT( CLK_KEY:IN STD_LOGIC; SEC_EN,MIN_EN,HOUR_EN, DAY_EN,MON_EN,YEAR_EN, WEEK_EN:O

32、UT STD_LOGIC; CURRUT_MONTH_DAYS:IN STD_LOGIC_VECTOR(4 DOWNTO 0); KEY:IN STD_LOGIC_VECTOR(1 DOWNTO 0); SEC_CUR:IN STD_LOGIC_VECTOR(5 DOWNTO 0); HOUR_CUR:IN STD_LOGIC_VECTOR(4 DOWNTO 0); MIN_CUR:IN STD_LOGIC_VECTOR(5 DOWNTO 0); YEAR_CUR:IN STD_LOGIC_VECTOR(6 DOWNTO 0); MON_CUR:IN STD_LOGIC_VECTOR(3 DO

33、WNTO 0); DAY_CUR:IN STD_LOGIC_VECTOR(4 DOWNTO 0); WEEK_CUR:IN STD_LOGIC_VECTOR(2 DOWNTO 0); SEC,MIN:BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0); HOUR:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0); YEAR:BUFFER STD_LOGIC_VECTOR(6 DOWNTO 0); MON:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0); DAY:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0

34、); WEEK:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0);END ENTITY TZKZQ;ARCHITECTURE ART4 OF TZKZQ IS TYPE STATETYPE IS(NORMAL,SEC_SET,MIN_SET,HOUR_SET,DAY_SET,MON_SET,YEAR_SET,WEEK_SET); SIGNAL MODE:STATETYPE; BEGIN PROCESS(KEY,CLK_KEY)IS BEGIN IF CLK_KEY'EVENT AND CLK_KEY='1'THEN IF KEY="01&

35、quot;THEN SEC_EN<='1'MIN_EN<='1'HOUR_EN<='1' DAY_EN<='1'MON_EN<='1'YEAR_EN<='1' WEEK_EN<='1' CASE MODE IS WHEN NORMAL=> MODE<=SEC_SET;SEC<=SEC_CUR;SEC_EN<='0' WHEN SEC_SET=>MODE<=MIN_SET;MIN<=MI

36、N_CUR;SEC_EN<='1'-MIN<='0' WHEN MIN_SET=>MODE<=HOUR_SET; HOUR<=HOUR_CUR;MIN_EN<='1'HOUR_EN<='0' WHEN HOUR_SET=>MODE<=DAY_SET; DAY<=DAY_CUR;HOUR_EN<='1'DAY_EN<='0' WHEN DAY_SET=>MODE<=MON_SET; MON<=MON_CUR;DA

37、Y_EN<='1'MON_EN<='0' WHEN MON_SET=>MODE<=YEAR_SET; YEAR<=YEAR_CUR;MON_EN<='1'YEAR_EN<='0' WHEN YEAR_SET=>MODE<=WEEK_SET; WEEK<=WEEK_CUR;YEAR_EN<='1'WEEK_EN<='0' WHEN WEEK_SET=>MODE<=NORMAL; END CASE; ELSIF KEY=

38、"10"THEN CASE MODE IS WHEN SEC_SET=>SEC_EN<='0' IF SEC="111011"THEN SEC<="000000"-IF>59 ELSE SEC<=SEC+1; END IF; WHEN MIN_SET=>MIN_EN<='0' IF MIN="111011"THEN MIN<="000000"-IF>59 ELSE MIN<=MIN+1; END IF;

39、WHEN HOUR_SET=>HOUR_EN<='0' IF HOUR="11000"THEN HOUR<="00000"-IF>23 ELSE HOUR<=HOUR+1; END IF; WHEN DAY_SET=>DAY_EN<='0' IF DAY=CURRUT_MONTH_DAYS THEN DAY<="00001" ELSE DAY<=DAY+1; END IF; WHEN MON_SET=>MON_EN<='0'

40、; IF MON="1100" THEN MON<="0001"-IF>12 ELSE MON<=MON+1; END IF; WHEN YEAR_SET=>YEAR_EN<='0' IF YEAR="1100011" THEN YEAR<="0000000"-IF>99 ELSE YEAR<=YEAR+1; END IF; WHEN WEEK_SET=>WEEK_EN<='0' IF WEEK="111"

41、; THEN WEEK<="001"-IF>7 ELSE WEEK<=WEEK+1; END IF; WHEN OTHERS=>NULL; END CASE; END IF; END IF; END PROCESS;END ARCHITECTURE ART4;7.3、CNT60计数模块的VHDL源程序-CNT60.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT60 IS PORT(LD:IN STD_LOGIC; CLK:IN

42、 STD_LOGIC; DATA:IN STD_LOGIC_VECTOR(5 DOWNTO 0); NUM:BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0); CO:OUT STD_LOGIC);END ENTITY CNT60;ARCHITECTURE ART1 OF CNT60 IS BEGIN PROCESS(CLK,LD)IS BEGIN IF(LD='0')THEN NUM<=DATA; ELSIF CLK'EVENT AND CLK='1'THEN IF NUM="111011"THEN NUM

43、<="000000"CO<='1' ELSE NUM<=NUM+1;CO<='0' END IF; END IF; END PROCESS;END ARCHITECTURE ART1;7.4 、CNT30计时电路的VHDL源程序-CNT30.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT30A IS PORT(LD:IN STD_LOGIC; CLK: IN STD_LOGIC; YEAR:IN

44、 STD_LOGIC_VECTOR(6 DOWNTO 0); MONTH:IN STD_LOGIC_VECTOR(3 DOWNTO 0); DATA:IN STD_LOGIC_VECTOR(4 DOWNTO 0); NUM:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0); CURRUT_MONTH_DAYS:OUT STD_LOGIC_VECTOR(4 DOWNTO 0); CO:OUT STD_LOGIC);END ENTITY CNT30A;ARCHITECTURE ART2 OF CNT30A IS SIGNAL TOTAL_DAYS:STD_LOGIC_VECT

45、OR(4 DOWNTO 0); BEGIN PROCESS(CLK,LD)IS VARIABLE IS_RUNYEAR:STD_LOGIC; BEGIN CASE YEAR IS WHEN"0000000"=>IS_RUNYEAR:='1'-0 WHEN"0000100"=>IS_RUNYEAR:='1'-4 WHEN"0001000"=>IS_RUNYEAR:='1'-8 WHEN"0001100"=>IS_RUNYEAR:='1&#

46、39;-12 WHEN"0010000"=>IS_RUNYEAR:='1'-16 WHEN"0010100"=>IS_RUNYEAR:='1'-20 WHEN"0011000"=>IS_RUNYEAR:='1'-24 WHEN"0011100"=>IS_RUNYEAR:='1'-28 WHEN"0100000"=>IS_RUNYEAR:='1'-32 WHEN"0100100&

47、quot;=>IS_RUNYEAR:='1'-36 WHEN"0101000"=>IS_RUNYEAR:='1'-30 WHEN"0101100"=>IS_RUNYEAR:='1'-44 WHEN"0110000"=>IS_RUNYEAR:='1'-48 WHEN"0110100"=>IS_RUNYEAR:='1'-52 WHEN"0111000"=>IS_RUNYEAR:=

48、9;1'-56 WHEN"0111100"=>IS_RUNYEAR:='1'-60 WHEN"1000000"=>IS_RUNYEAR:='1'-64 WHEN"1000100"=>IS_RUNYEAR:='1'-68 WHEN"1001000"=>IS_RUNYEAR:='1'-72 WHEN"1001100"=>IS_RUNYEAR:='1'-76 WHEN"101

49、0000"=>IS_RUNYEAR:='1'-80 WHEN"1010100"=>IS_RUNYEAR:='1'-84 WHEN"1011000"=>IS_RUNYEAR:='1'-88 WHEN"1011100"=>IS_RUNYEAR:='1'-92 WHEN"1100000"=>IS_RUNYEAR:='1'-96 WHEN OTHERS =>IS_RUNYEAR:='0

50、9;END CASE;CASE MONTH IS WHEN"0000"=>TOTAL_DAYS<="11111"-1YUE WHEN"0011"=>TOTAL_DAYS<="11111"-3YUE WHEN"0101"=>TOTAL_DAYS<="11111"-5YUE WHEN"0111"=>TOTAL_DAYS<="11111"-7YUE WHEN"1000"=&g

51、t;TOTAL_DAYS<="11111"-8YUE WHEN"1010"=>TOTAL_DAYS<="11111"-10YUE WHEN"1100"=>TOTAL_DAYS<="11111"-12YUE WHEN"0100"=>TOTAL_DAYS<="11110"-4YUE WHEN"0110"=>TOTAL_DAYS<="11110"-6YUE WHEN&q

52、uot;1001"=>TOTAL_DAYS<="11110"-9YUE WHEN"1011"=>TOTAL_DAYS<="11110"-11YUE WHEN"0010"=>IF(IS_RUNYEAR='1')THEN TOTAL_DAYS<="11101"-29 ELSE TOTAL_DAYS<="11100"-28 END IF; WHEN OTHERS =>NULL;END CASE;IF(LD=&

53、#39;0')THEN NUM<=DATA;ELSIF CLK'EVENT'ANDCLK='1'THEN CURRUT_MONTH_DAYS<=TOTAL_DAYS; IF NUM=TOTAL_DAYS THEN NUM<="00001"CO<='1' ELSE NUM<=NUM+1;CO<='1' END IF;END IF;END PROCESS;END ARCHITECTURE ART2;7.5、系统总体组装电路的VHDL源程序- COPYRIGHT (C) 1

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