异步、同步数据接口设计

1、异步数据接口设计一、设计要求1、输入数据以学号重复循环组成， 学号的每一位以一个字节 （8bit ） 表示，以字节串行方式，高位字节先输入，低位字节后输入。字节输 入时钟频率30MHz频率初始相位自定义。2、输出数据：以字节串行方式输出学号，高位字节先输出，低位 字节后输出。 学号的输出必须连续不间断地完整输出一个学号， 相邻 学号间可插入多个H“FF”字节。字节输出时钟频率100MHz频率初 始相位自定义。3、分别以同步FIFO和异步FIFO实现上述接口设计。完成硬件描 述语言设计、综合、时序仿真验证。分别对以上两种实现方案进行性 能分析并比较各自的优缺点。二、设计分析1、同步FIFO由同一

2、个时钟控制FIFO的读写操作，所以设计相对 简单，对于实现上述接口设计，可以简单划分为读控制单元、写控制 单元、数据转存单元实现。其中读控制单元为简单的逻辑控制单元， 主要用于产生读信号， 写控制单元类似于读控制单元， 主要用于产生 写状态信号，数据转存单元主要由存储器组成，当写信号有效，将 8bit 的输入数据写入存储器（存储器未满情形下） ，当读信号有效， 从存储器中读出 8bit 的数据（存储器未空情形下） 。结构图如图 1 所示:d|elucM ns-sartlread cairrorizbGkreseiI< TillI叽曲向 Qiiljull也时 mo 刃欝 m ptyT 丄*

3、订牡EmohrjHI3_WITT D|writ! Lu nil J U1图1、同步FIFO的接口设计结构图2、异步FIFO分别利用读时钟和写时钟控制 FIFO的读写操作，因 为涉及到跨时钟域设计，相对于同步 FIFO时序要复杂。如图2结构 图所示，设计划分为数据通道单元、控制单元、状态控制单元。数据 通道单元类似于数据转存单元，控制数据的流入流出存储器。控制单 元根据输入产生读写控制标志，从而控制其他两个模块的读写。状态 控制单元主要用于产生标志存储器当前状态（空、满等）的各个标志 位，同时产生读写时访问存储器需要的指针。 其基本结构图如图2所示:图2、异步FIFO的接口设计结构图三、设计实现

4、1、基于上述同步FIFO接口设计的分析，分模块对电路进行HDL建模，HDLI苗述如下:(1) 读操作控制模块：module read_control (input clock,reset,input stk_empty, output reg read);always (posedge clock or posedge reset) if(reset) read<=1'b0;else if(!stk_empty) read<=1'b1;else read<=1'b0;endmodule(2) 写操作控制模块:module write_control (

5、input clock,reset,input stk_full, output reg write );always (posedge clock or posedge reset) if(reset) write<=1'b0;else if(!stk_full)write<=1'b1;else write<=1'b0;endmodule(3) 数据转换模块:module fifo_syn #(parameter stk_width=8,half_stk_depth=8,stk_depth=16,ptr_width=4)(clock,reset,da

6、ta_in,write,read,data_out,stk_full,stk_almost_full,stk_half_full,stk_almost_empty,stk_empty);input clock,reset,write,read;input stk_width-1:0 data_in;output stk_width-1:0 data_out;/reg stk_full,stk_almost_full,stk_half_full,stk_alm reg stk_width-1:0 data_out;reg ptr_width-1:0write_ptr,read_ptr;reg p

7、tr_width:0ptr_gap;reg stk_width-1:0stackstk_depth-1:0;assign stk_full=(ptr_gap=stk_depth)?1'b1:1'b0; assign stk_almost_full=(ptr_gap=(stk_depth-2)?1'b1:1'b0; assign stk_half_full=(ptr_gap=half_stk_depth)?1'b1:1'b0; assign stk_almost_empty=(ptr_gap=2)?1'b1:1'b0;assign

8、stk_empty=(ptr_gap=0)?1'b1:1'b0;always (posedge clock or posedge reset) if(reset)begin write_ptr<=1'b0; read_ptr<=1'b0; ptr_gap<=1'b0;endelsebegin if(write)&&(!stk_full)&&(!read) beginstackwrite_ptr<=data_in; write_ptr<=write_ptr+1'b1; ptr_gap&l

9、t;=ptr_gap+1'b1;endelse if(read)&&(!stk_empty)&&(!write) begindata_out<=stackread_ptr; read_ptr<=read_ptr+1'b1; ptr_gap<=ptr_gap-1'b1;endelse if(write)&&(read)&&(stk_full)&&(!stk_empty) begindata_out<=stackread_ptr; read_ptr<=read_pt

10、r+1'b1; ptr_gap<=ptr_gap-1'b1;endelse if(write)&&(read)&&(stk_empty)&&(!stk_full) beginstackwrite_ptr<=data_in; write_ptr<=write_ptr+1'b1; ptr_gap<=ptr_gap+1'b1;endelse if(write)&&(read)&&(!stk_full)&&(!stk_empty) beginstack

11、write_ptr<=data_in; write_ptr<=write_ptr+1'b1; data_out<=stackread_ptr; read_ptr<=read_ptr+1'b1;endendendmodule(4) 顶层例化：module top_fifo #(parameter stk_width=8) (clock,reset,data_in,data_out,stk_full,stk_almost_full,stk_half_full, stk_almost_empty,stk_empty);input clock,reset;inp

12、ut stk_width-1:0 data_in;output stk_full,stk_almost_full,stk_half_full,stk_almost_empty,stk_empty;output stk_width-1:0 data_out;wire write_net,read_net;write_control U1(clock,reset,stk_full,write_net);read_control U2( clock,reset,stk_empty,read_net); fifo_synU3(clock,reset,data_in,write_net,read_net

13、,data_out,stk_full,stk_almost_full ,stk_half_full,stk_almost_empty,stk_empty);endmodule(5)testbench 模块：'timescale 1ns/1nsmodule tb_top_fifo #(parameter stk_width=8);reg clock,reset;reg stk_width-1:0 data_in;wire stk_full,stk_almost_full,stk_half_full,stk_almost_empty,stk_empty;wire stk_width-1:0

14、 data_out; top_fifoU(clock,reset,data_in,data_out,stk_full,stk_almost_full,stk_half_full, stk_almost_empty,stk_empty);initialbeginclock=0;reset=0;data_in=0;endalways #5 clock=clock;initialbegin#10 reset=1;#10 reset=0;endinitialbegin#20repeat(10)begin#10 data_in=8'd2;#10 data_in=8'd0;#10 data

15、_in=8'd1;#10 data_in=8'd3;#10 data_in=8'd2;#10 data_in=8'd2;#10 data_in=8'd2;#10 data_in=8'd4;#10 data_in=8'd0;#10 data_in=8'd2;#10 data_in=8'd3;#10 data_in=8'd2;#10 data_in=8'd15;#10 data_in=8'd15;endendinitial #1000 $stop;HDLendmodule2、基于上述异步 FIFO 接口

16、设计的分析，分模块对电路进行建模，HDLI苗述如下：(1) 控制单元module control_unit(inout read,input write,input stk_empty,input stk_full,output read_fr_stk,output write_to_stk);assign write_to_stk=(write && (!stk_full);assign read_fr_stk=(read && (!stk_empty);endmodule(2) 数据通道单元Module datapath_unit #(parameter s

17、tack_width=8,stack_depth=16,poiter_width=4) (input clk_write, input clk_read, input rst, input read_fr_stk, input write_to_stk,input poiter_width-1:0write_ptr, input poiter_width-1:0read_ptr, inputstack_width-1:0 data_in, output reg stack_width-1:0 data_out); reg stack_width-1:0 stackstack_depth-1:0

18、;integer i;always (posedge clk_write or posedge rst)beginif(rst)for(i=0;i<=15;i=i+1)begin stacki<=8'd0; end else if (write_to_stk) beginstackwrite_ptr<=data_in;endendalways (posedge clk_read /*or posedge rst*/)beginif (read_fr_stk)begindata_out<=stackread_ptr;endend endmodule(3) 状态控制

19、单元 module status_unit #(parameter stack_depth=16,stack_half_depth=8,poiter_width=4)(input clk_write, input clk_read, input rst, input read_fr_stk, input write_to_stk, output reg poiter_width-1:0write_ptr, output reg poiter_width-1:0read_ptr, output stk_full, output stk_almost_full, output stk_half_f

20、ull, output stk_almost_empty, output stk_empty);reg poiter_width:0 write_cnt;reg poiter_width:0 read_cnt;wire poiter_width:0 ptr_gap;assign ptr_gap=write_cnt-read_cnt;assign stk_full=(ptr_gap=stack_depth)?1'b1:1'b0;assign stk_almost_full=(ptr_gap=stack_depth-2)?1'b1:1'b0; assign stk_

21、half_full=(ptr_gap=stack_half_depth)?1'b1:1'b0; assign stk_almost_empty=(ptr_gap=2)?1'b1:1'b0;assign stk_empty=(ptr_gap=0)?1'b1:1'b0;always (posedge clk_write or posedge rst)beginif(rst)beginwrite_cnt<=5'd0;endelse if (write_to_stk) begin write_cnt<=write_cnt+5'

22、d1; write_ptr<=write_cntpoiter_width-1:0; endendalways (posedge clk_read or posedge rst)beginif(rst)beginread_cnt<=5'd0;endelse if (read_fr_stk) begin read_cnt<=read_cnt+5'd1; read_ptr<=read_cntpoiter_width-1:0; endend endmodule(4) 顶层设计module top_fifo_asyn #(parameter stack_width

23、=8,poiter_width=4)(input clk_write, input clk_read, input rst, input write, input read, inputstack_width-1:0 data_in, output stk_full, output stk_almost_full, output stk_half_full,output stk_almost_empty,output stk_empty,output stack_width-1:0 data_out);wire read_fr_stk;wire write_to_stk;wire poiter

24、_width-1:0write_ptr;wire poiter_width-1:0read_ptr;control_unit U1(read,write,stk_empty,stk_full,read_fr_stk,write_to_stk); datapath_unitU2(clk_write,clk_read,rst,read_fr_stk,write_to_stk,write_ptr,read_ptr,data_ in,data_out);status_unit U3(clk_write,clk_read,rst,read_fr_stk,write_to_stk,write_ptr,re

25、ad_ptr,stk_f ull,stk_almost_full,stk_half_full,stk_almost_empty,stk_empty);endmodule(5) testbench timescale 1ns/1nsmodule tb_top_fifo_asyn #(parameter stack_width=8);reg clk_write;reg clk_read;reg rst;reg write;reg read;regstack_width-1:0 data_in;wire stack_width-1:0 data_out;wire stk_full,stk_almos

26、t_full,stk_half_full,stk_almost_empty,stk_empty; top_fifo_asynU(clk_write,clk_read,rst,write,read,data_in,stk_full,stk_almost_full, stk_half_full,stk_almost_empty,stk_empty,data_out);initialbegin clk_read=0; clk_write=0; rst=0; write=0; read=0; data_in=0;endalways #17 clk_write=clk_write; always #5

27、clk_read=clk_read; initialbegin#10 rst=1;#10 rst=0;end initialfork#34 write=1;#1020 write=0;#1496 write=1;#580 read=1;#1000 read=0;#1500 read=1;join initialbegin#34 repeat(10) begin#34 data_in=8'd2;#34 data_in=8'd0;#34 data_in=8'd1;#34 data_in=8'd3;#34 data_in=8'd2;#34 data_in=8&

28、#39;d2;#34 data_in=8'd2;#34 data_in=8'd4;#34 data_in=8'd0;#34 data_in=8'd2;#34 data_in=8'd3;#34 data_in=8'd2;#34 data_in=8'hFF;#34 data_in=8'hFF;endend initial #2000 $stop; endmodule四、设计仿真1、选择合适ALTERA勺FPGA芯片，对上述两种设计进行编译、分析、综合。然后利用MODELSI进行仿真验证。2、同步FIFO实现的接口设计，基于上述TESTBENCH件，MODELSIM仿真验证结果如图 3 所示Iffacidc: ft rati