XILINX Microblaze的六个实验,开发平台为EDK10.1之四

1、For Academic Use OnlyLab 4- Writing Basic Software ApplicationsTargeting MicroBlaze on the Spartan-3E Starter Kit IntroductionThis lab guides you through the process of writing a basic software application. The softwarewill write to the LEDs on the Spartan-3E starter kit. You will add an XPS BRAM co

2、ntroller andmodify the linker script to place the text section in the BRAM. Finally, you will verify that thedesign operates as expected in hardware.ObjectivesAfter completing this lab, you will be able to:Add an internal Block RAM memory controllerWrite a basic application to access an IP periphera

3、lDevelop a linker scriptPartition the executable sections onto both the LMB and PLB memory spacesGenerate a bit fileDownload the bit file and verify on the Spartan-3E starter kitProcedureExtend the processor system created in lab3 by adding a memory controller (see figure 4-1 andthe writing a basic

4、software application to access the LEDs on the Spartan-3E starter kit. Thesteps are listed below:1.Add an internal BRAM2.Update a basic software application3.Analyze assembled object files4.Verify the deisgn in hardwareFigure 4-1. Design Updated from Previous LabFor each procedure within a primary s

5、tep, there are general instructions (indicated by thesymbol. These general instructions only provide a broad outline for performing the procedure. Below these general instructions, you will find accompanying step-by-step directions and illustrated figures that provide more detail for performing the

6、procedure. If you feel confident about completing a procedure, you can skip the step-by-step directions and move on to the next general instruction.LMB BRAM CNTLRLMB BRAM CNTLRBRAMPLBMDMUARTMicroBlazeGPIO GPIO MYIPGPIOBRAMXPS BRAM CNTLRMPMCCNTLRAdd an Internal BRAM Step 1 Add a BRAM controller and B

7、RAM to the design.If you wish to continue using the design that you created in Lab 3, create a lab4 folder in the c:xupembeddedlabs directory and copy the contents from lab3 to lab4, otherwise copy thecontent of lab3 folder from the completed folderOpen XPS by selecting Start Programs Xilinx ISE Des

8、ign Suite 10.1i EDK Xilinx Platform StudioSelect Open a recent project, and browse to lab4 folder to open the projectFrom the IP catalog, add the following IP to the embedded hardware designXPS BRAM Controller 1.00.aBlock RAM (BRAM block 1.00.aChange the instance names and connect the BRAM controlle

9、r to the PLB and connect the BRAM to the BRAM controller (see Figure 4-2. Figure 4-2. Add internal XPS memory controllerSelect a size of 8K for the XPS BRAM controller and click Generate Addresses Figure 4-3. Specify Size and Address of Internal BRAM Memory ControllerUpdate a Basic Software Applicat

10、ion Step 2 Run LibGen to generate xparameters.h file which defines various symbolicparameters. Modify a software program to display the DIP switch settings on theLEDs.Run libgen by seelcting Software Generate Libraries and BSPs to generatexparameters.h fileLibGen writes the xparameters.h file, which

11、 provides critical information for driver function calls.In the Applications tab, remove lab3.c and add lab4.c to the TestApp_Memory projectYou will extend the functionality in lab4.c by adding code to display switch settings on theLEDs.Open the GPIO API documentation by right-clicking on LEDs_8Bit

12、peripheral in the System Assembly View and selecting Driver: gpio_v2_12_a View API DocumentationView the various C and Header files associated with the GPIO by selecting File List at the top of the page.Click the header file xgpio.h and review the list of available function calls for the GPIOThe fol

13、lowing steps must be performed in the software application to enable writing to the GPIO: 1 Initialize the GPIO, 2 Set data direction, and 3 Write the dataFind the descriptions for the following functions by clicking links:XGpio_Initialize (XGpio *InstancePtr, u16 DeviceIdInstancePtr is a pointer to

14、 an Xgpio instance. The memory the pointer references must be pre-allocated by the caller. Further calls to manipulate the component through theXGpio API must be made with this pointer.DeviceId is the unique ID of the device controlled by this XGpio component. Passing ina device ID associates the ge

15、neric XGpio instance to a specific device, as chosen by thecaller or application developer.XGpio_SetDataDirection (XGpio * InstancePtr, unsignedChannel, u32 DirectionMaskInstancePtr is a pointer to the XGpio instance to be worked on.Channel indicates the channel of the GPIO (1 or 2 to operate onDire

16、ctionMask is a bit mask specifying which discretes are input and which are output.Bits set to 0 are output and bits set to 1 are input.XGpio_DiscreteWrite (XGpio *InstancePtr, unsigned channel,u32 dataInstancePtr is a pointer to the XGpio instance to be worked on.Channel indicates the channel of the

17、 GPIO (1 or 2 to operate onData is the data written to the discrete registers.Open the header file xparameters.h by double-clicking on Generated Header:microblaze_0/include/xparameters.h under the microblaze_0 instance for the TestApp_Memory project in the Applications tab. Figure 4-4. Double-Click

18、the Generated Header FileIn the xparameters.h file, find the following #define used to identify the LEDs_8Bit peripheral:#define XPAR_LEDS_8BIT_DEVICE_IDNote: The LEDS_8BIT matches the instance name assigned in the MHS file for this peripheral.This #define can be used in the XGpio_Intialize function

19、 call.Modify your C code to echo the dip switch settings on the LEDS (Figure 4-5 and save theapplication.Note: The number might be different Figure 4-5. Partially Completed C FileClick the compile button to compile the program.Analyze Assembled Object Files Step 3 Analyze the assembled object files

20、and how using the objdump utility links them. Start the Cygwin shell, execute the object dump on the executable and analyze the output.Launch the Cygwin shell by going to Project Launch EDK shell. Change the directory to .TestApp_Memory by using the cd command.You can determine your directory path b

21、y using the pwd command.Type mb-objdump h executable.elfat the prompt in the Xygwin shell window to list various sections of the program, along with the starting address and size of each section You should see results similar to that below:Figure 4-6. Object Dump Results - .text in XPS BRAM spaceNot

22、e the start address of the text section resides in the lmb_bram spaceChange the location of the text section so that it resides in the PLB memory. Recompile the code, re-execute the objdump command, and analyze the output. Right-click on Project:TestApp_Memory in the Applications tab and select Gene

23、rate Linker Script. Figure 4-7. Generate Linker ScriptSelect xps_bram_if_cntlr_0 as the memory space for the instructions (.text section Figure 4-8. Select XPS BRAM Space for the .text SectionMake sure that the Output Linker Script path is set to the TestApp_Memory directory andclick OK Recompile th

24、e program and execute the mb-objdump command in the Xygwin shellFigure 4-9. Object Dump Results - .text in XPS BRAM spaceVerify in Hardware Step 5Connect and power the board. Generate the bitstream and download to hardware. Connect and power the boardOpen a hyperterminal session with the following s

25、ettings Baud rate: 115200 Data bits: 8 Parity: none Stop bits: 1 Flow control: noneGenerate and download bitstream.Flip the DIP switches and verify that the LEDs will light according to the switch settings. Verify that you see the results of the DIP switch and Push button settings in hyperterminalNo

26、te the start address of the text section resides in the xps_bram space Figure 4-10. DIP Switch and Push Button settings displayed in hyperterminal Note: Setting the DIP switches and push buttons will change the results displayed Change xil_printf function call to printf. Re-compile the code and obse

27、rve that the XPS BRAM space is not sufficient. Generate linker script to target the .text section to external memory (DDR_SDRAM.In the text editor, change the xil_printf function call to printfCompile the code and observe the output in the console window Observe in the console window that the .text

28、section is too big and sections overlapSelect Software Generate Linker ScriptTarget .text section to DDR_SDRAM memory and click OK Figure 4-11. Retargeting .text section to External MemoryA warning message will appear indicating that the linker script already exist. Click OK tooverwrite. Set XMD opt

29、ion with default values. Initialize BRAM with bootloop application.As the .text section is targeted to external memory, it must be loaded using XMDSelect Debug XMD Debug Options and click OK to accept the default settingsIn the Application tab, right-click on TestApp_Memory and deselect Mark to Init

30、ialize BRAMs so that this application should not be put in the BRAM Figure 4-12: Deselect TestApp_Memory to be Initialized in BRAMSimilalry, right-click on Default:microblaze_0_bootloop and make the BRAM to be initializedSelect Debug Launch XMD to start the XMD debugger which will make connection wi

31、th the microblaze processor in FPGAIn the XMD window, type dow TestApp_Memory/executable.elfThis will download the application in the external memory.In the XMD window, type con to execute the programObserve the HyperTerminal window as the program executes. Play with dip switches andobserve the LEDs

32、In the XMD widnow, type stop to stop the program execution, and then type exit to close the XMD windowClose the project and XPSConclusionUse Xilinx Platform Studio to define, develop, and integrate the software components of theembedded system. You can define a device driver interface for each of th

33、e peripherals and theprocessor. XPS creates an MSS file that represents the software side of the processor system.You can then develop and compile peripheral-specific functional software and generate theexecutable file from the compiled object codes and libraries. If needed, you can also use a linke

34、rscript to target various segments in various memories. You can edit the linker script to controlplacement of various code segments into target memory. When the application is too big to fit inthe internal BRAM, you can download the application in external memory using XMD, and thenexecute the progr

35、am.AnswersA1.List the created subfolders, their contents, and their possible purposes under the microblaze_0 folder inthe lab4 folder.code empty folder this is where the executable file will be placedinclude several header files for included peripherals and functionslib library files lbc, libm, libx

36、illibsrc source for all the librariesCompleted MHS FileA# # Created by Base System Builder Wizard for Xilinx EDK 10.1.01 Build EDK_K_SP1.3# Thu Jun 05 12:21:01 2008# Target Board: Xilinx Spartan-3E Starter Board Rev D# Family: spartan3e# Device: XC3S500e# Package: FG320# Speed Grade: -4# Processor:

37、microblaze_0# System clock frequency: 50.00 MHz# On Chip Memory : 8 KB# Total Off Chip Memory : 64 MB# - DDR_SDRAM = 64 MB# PARAMETER VERSION = 2.1.0PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX, DIR = IPORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX, DIR = OPORT fpga_0_LEDs_8Bit_GPIO_d_out_

38、pin = fpga_0_LEDs_8Bit_GPIO_d_out, DIR = O, VEC = 0:7PORT fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O =fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O, DIR = IOPORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDR

39、AM_DDR_Clk_n, DIR = OPORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC = 12:0PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin =fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = 1:0PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = OPORT fpga_0_DDR_SDRAM_DDR_CE_pin =

40、 fpga_0_DDR_SDRAM_DDR_CE, DIR = O PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = OPORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = OPORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = OPORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM

41、_DDR_DM, DIR = O, VEC = 1:0PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = 1:0PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = 15:0PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ =50000000PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARIT

42、Y = 1, SIGIS = RST PORT push_GPIO_in_pin = push_GPIO_in, DIR = I, VEC = 0:3PORT dip_GPIO_in_pin = dip_GPIO_in, DIR = I, VEC = 0:3PORT lcd_ip_0_lcd_pin = lcd_ip_0_lcd, DIR = O, VEC = 0:6BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER C_INTERCONNECT = 1 PARAMETER HW_VER = 7.10.b PARAMETER

43、 C_DEBUG_ENABLED = 1 PARAMETER C_AREA_OPTIMIZED = 1 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DPLB = mb_plb BUS_INTERFACE IPLB = mb_plb BUS_INTERFACE DEBUG = microblaze_0_dbg PORT MB_RESET = mb_reset END BEGIN plb_v46 PARAMETER INSTANCE = mb_plb PARAMETER HW_VER = 1.02.a PORT

44、 PLB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset EN

45、D BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_port END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 2.10.a

46、PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_port END BEGIN bram_block PARAMETER INSTANCE = lmb_bram Writing Basic Software Applications Lab: MicroBlaze Processor xup 4-17 PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA =

47、ilmb_port BUS_INTERFACE PORTB = dlmb_port END BEGIN xps_uartlite PARAMETER INSTANCE = RS232_DCE PARAMETER HW_VER = 1.00.a PARAMETER C_BAUDRATE = 115200 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000 PARAMETER C_BASEADDR = 0x840

48、00000 PARAMETER C_HIGHADDR = 0x8400ffff BUS_INTERFACE SPLB = mb_plb PORT RX = fpga_0_RS232_DCE_RX PORT TX = fpga_0_RS232_DCE_TX END BEGIN xps_gpio PARAMETER INSTANCE = LEDs_8Bit PARAMETER HW_VER = 1.00.a PARAMETER C_GPIO_WIDTH = 8 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 0 PARAMETER C_ALL_INPU

49、TS = 0 PARAMETER C_BASEADDR = 0x81440000 PARAMETER C_HIGHADDR = 0x8144ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out END BEGIN mpmc PARAMETER INSTANCE = DDR_SDRAM PARAMETER HW_VER = 4.01.a PARAMETER C_NUM_PORTS = 1 PARAMETER C_MEM_PARTNO = MT46V32M16-6 PARAMETER C_SPE

50、CIAL_BOARD = S3E_STKIT PARAMETER C_MEM_BANKADDR_WIDTH = 2 PARAMETER C_MEM_DATA_WIDTH = 16 PARAMETER C_MEM_DQS_WIDTH = 2 PARAMETER C_MEM_DM_WIDTH = 2 PARAMETER C_MEM_TYPE = DDR PARAMETER C_PIM0_BASETYPE = 2 PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000 PARAMETER C_SPLB0_NATIVE_DWIDTH = 32 PARAMETER C_MPMC_

51、BASEADDR = 0x8c000000 PARAMETER C_MPMC_HIGHADDR = 0x8fffffff BUS_INTERFACE SPLB0 = mb_plb PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr PORT DDR_CAS_n = fpga_0_DDR_SDRAM_

52、DDR_CAS_n PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n Writing Basic Software Applications Lab: MicroBlaze Processor xup 4-18 PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM PORT DDR_DQS =

53、fpga_0_DDR_SDRAM_DDR_DQS PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O PORT MPMC_Clk0 = DDR_SDRAM_mpmc_clk_s PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s PORT

54、MPMC_Rst = sys_periph_reset END BEGIN clock_generator PARAMETER INSTANCE = clock_generator_0 PARAMETER HW_VER = 2.01.a PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER C_CLKIN_FREQ = 50000000 PARAMETER C_CLKOUT0_FREQ = 50000000 PARAMETER C_CLKOUT0_BUF = TRUE PARAMETER C_CLKOUT0_PHASE = 0 PARAMETER C_CLKOUT0

55、_GROUP = NONE PARAMETER C_CLKOUT1_FREQ = 100000000 PARAMETER C_CLKOUT1_BUF = TRUE PARAMETER C_CLKOUT1_PHASE = 0 PARAMETER C_CLKOUT1_GROUP = DCM0 PARAMETER C_CLKOUT2_FREQ = 100000000 PARAMETER C_CLKOUT2_BUF = TRUE PARAMETER C_CLKOUT2_PHASE = 90 PARAMETER C_CLKOUT2_GROUP = DCM0 PORT CLKOUT0 = sys_clk_s PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_s PORT CLKOUT2 = DDR_SDRAM_mpmc_clk_90_s PORT CLKIN = dcm_clk_s PORT LOCKED = Dcm_all_locked PORT RST = net_gnd END BEGIN mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 1.00.b PARAMETER C_MB_DBG_PORTS = 1 PARAMET