带使能和同步清控制的增减位进制计数器

1、实验六 计数器二、实验目的1、以计数器为例，掌握时序电路设计方法。2、熟练掌握ISE软件进行FPGA开发的过程以及实验箱的使用方法。3、了解ISE设计报告中电路资源利用率情况分析。4、掌握使用VHDL创建测试文件的方法。二、设计要求1、 设计一个带使能和同步清0控制的增 1减 1七位二进制计数器；计数结果由两位数 码管显示。2、输入时钟信号接时钟电路的相应输出，复位等控制信号接拨码开关或按键，输出信 号接七段数码管。三、实验步骤1、启动ISE集成开发环境，创建工程并输入设计源文件。2、对设计进行时序仿真，分析设计的正确性。3、 锁定引脚，完成设计实现过程。并在实验箱上连线，利用iMPACT进行

2、程序下载。4、在实验箱上验证计数器的功能，观察并记录实验结果。四、实验报告预习要求：1、阅读教材第二章 2.3节，熟悉ISE软件设计模板使用方法。2、写出计数器的 VHDL源程序。library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity counter isport(clk,clk1,ce, reset, dir: IN STD_LOGIC;a,b,c,d,e,f,g:out std_logic;co: out std_logic_ve

3、ctor(1 downto 0);end counter;architecture Behavioral of counter issignal count_int : STD_LOGIC_VECTOR(6 downto 0);signal s:std_logic_vector(6 downto 0);signal hex:std_logic_vector(3 downto 0);beginprocess (clk)beginif clk'event and clk='1' thenif reset = '1' thencount_int <= (

4、 others=> '0');elseif ce = '1' thenif dir = '1' then count_int<=count_int + 1; else count_int<=count_int-1; end if; end if; end if; end if; end process; co<="01" when clk1='0' else "10" bi1<=count_int(3 downto 0)when clk1='0'

5、 else '0'&count_int(6 downto 4);process(hex)begincase hex iswhen"0000"=>s<="1111110"when"0001"=>s<="0110000"when"0010"=>s<="1101101"when"0011"=>s<="1111001"when"0100"=>s&l

6、t;="0110011"when"0101"=>s<="1011011"when"0110"=>s<="1011111"when"0111"=>s<="1110000"when"1000"=>s<="1111111"when"1001"=>s<="1111011"when"1010"=>s&l

7、t;="1110111"when"1011"=>s<="0011111"when"1100"=>s<="1001110"when"1101"=>s<="0111101"when"1110"=>s<="1001111"when"1111"=>s<="1000111"when others=>s<="

8、0000000"end case;end process;g<=s(0);f<=s(1);e<=s(2);d<=s(3);c<=s(4);b<=s(5);a<=s(6);end Behavioral;3、画出测试基准波形文件以及计数器的输出。End Tims: 6000 ns1DQ*JOO13001900250031D&370043D0IIIII1IIIIIIIII11刖lxQ J-LrLTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT-rLrLrLr1 T汕比1厂BLfl dr1yjl WSETt0 1 1B

9、LD dkl 侧0 J-LTLTTJTTTTTJ-LrLJTTTJ-LrTTTTTTTTTTTTTTTTTJ-LrLn-r01_TUlo0Q伽0D讪a0EI$C«41'Q|ZhQ- (2nfl004、写出实现测试基准波形输出的VHDL源代码。LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_ un sig ned.all;USE ieee .nu meric_std.ALL;ENTITY cou ntertest_vhd ISEND coun tertest_vhd;ARCHITECTURE behavio

10、r OF coun tertest_vhd IS-Comp onent Declarati on for the Un it Un der Test (UUT) COMPONENT coun ter7PORT(clk : IN std_logic;clk1 : IN std_logic;ce : IN std_logic;reset : IN std_logic;dir : IN std_logic;a : OUT std_logic;b : OUT std_logic;c : OUT std_logic;d : OUT std_logic;e : OUT std_logic;f : OUT

11、std_logic;g : OUT std_logic;co : OUT stdo gic_vector(1 dow nto 0);END COMPONENT;-I nputsSIGNAL clk :std_logic := 'O'SIGNAL clk1 :std_logic := '0'SIGNAL ce :std_logic := '0'SIGNAL reset :std_logic := '0'SIGNAL dir :std_logic := '1'3 / 6-OutputsSIGNAL a :std_log

12、ic;SIGNAL b :std_logic;SIGNAL c :std_logic;SIGNAL d :std_logic;SIGNAL e :std_logic;SIGNAL f :std_logic;SIGNAL g :std_logic;SIGNAL co: std_logic_vector(1 downto 0);BEGIN- Instantiate the Unit Under Test (UUT)uut: counter7 PORT MAP(clk => clk, clk1 => clk1, ce => ce, reset => reset, dir =&

13、gt; dir, a => a, b => b, c => c, d => d, e => e, f => f, g => g, co => co);tb : PROCESS BEGIN- Wait 100 ns for global reset to finishwait for 100ns;clk<='1' after 100ns,'0' after 200ns,'1' after 300ns,'0' after 400ns,'1' after 500ns,

14、'0' after 600ns,'1' after 700ns,'0' after 800ns,'1' after 900ns,'0' after 1000ns,'1' after 1100ns,'0' after 1200ns,'1' after 1300ns,'0' after 1400ns,'1' after 1500ns,'0' after 1600ns,'1' after 1700ns,'

15、;0' after 1800ns;clk1<='1' after 100ns,'0' after 200ns,'1' after 300ns,'0' after 400ns,'1' after 500ns,'0' after 600ns,'1' after 700ns,'0' after 800ns,'1' after 900ns,'0' after 1000ns,'1' after 1100ns,'

16、;0' after 1200ns,'1' after 1300ns,'0' after 1400ns,'1' after 1500ns,'0' after 1600ns,'1' after 1700ns,'0' after 1800ns;reset<= '1' after 100ns,'0' after 300ns; dir<='1'ce<='1' after 500ns; - Place stimulus h

17、ere wait; - will wait foreverEND PROCESS;END;实验记录：1、设计记录表，记录引脚锁定与连线情况。ISE软件实验箱端口名称芯片引脚号IO类型编号aB4OIO1bA4OIO2cD5OIO3dC5OIO4eA6OIO5fB6OIO6gE7OIO7elkD7IIO9clklC7IIO10eeF7IIO8co(1)E8OIO12co(0)F8OIO11dirA13IIO21resetB13IIO222、记录实验现象，分析实验结果。 功能仿真：NOW： 3000 ns1TI5ItoooI,I2000,iI ,3000胡少1OnnI Ir：nnL匚n匚1二I Il

18、Jtztutz丄Lif'dn训|也LJ1uLC匚* _1二t1匚二L1:ro二ir* '1二4IJ电,ILJirjorE二r-no匚n=时丽莎:亟莎:Zhi'：'c；zni：i同豳：话：垂組.门|1jcZZ-Jocuc匚二j匚也IK：0*nnntnoMtznoHo时序仿真:7F。3、查看设计报告，记录此计数器所用的逻辑资源。Device Ulilizati-oin.L«.(i c Utilii onUsedvkiliiiblieUiLili. z<ti anH«tC! (s)Jlijn'b*!* of Slic4 Flap79,312IXof <1 input LUIs23g.aiz1亀L«gic DiEtri.hTkti*iiITuntftr af ecc